Node Skipping Reaches New Heights

By Mark LaPedus
For years, silicon foundries have rolled out their respective leading-edge processes roughly on a two-year cadence.

The long-standing goal has been to keep foundry customers on a competitive price, power and performance curve. But as leading-edge chipmakers move from the 28nm node and beyond, the predictable process progression is changing. And the phenomenon of “node skipping” in the fabless-foundry world could reach new heights.

Two foundry vendors, GlobalFoundries and Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC), recently accelerated their respective 14nm-class finFET shipment schedules by a year or so. In effect, the companies have shrunk the process cadence between their planar 20nm and 3D-like finFET technologies to roughly a year.

Samsung is expected to follow a similar path. In many respects, the foundries appear to be luring customers into making the giant leap from 28nm (or above) processes to finFETs, thereby skipping 20nm. The reason is largely due to lackluster demand for 20nm planar, and they are aggressively marketing their finFET technologies right now.

Rival United Microelectronics Corp. (UMC) has a different strategy. UMC will move directly from 28nm planar to 14nm-class finFETs, bypassing the 20nm planar node. UMC recently licensed finFET technology from IBM, but it will stick with bulk CMOS. For its part, IBM will ramp up finFETs using silicon-on-insulator (SOI) technology.

The foundries are speeding up their finFET efforts for several reasons. First, there is a perception that the foundries are falling further behind Intel. The chip giant rolled out finFETs at 22nm and is offering the technology to select foundry customers. Intel plans to begin ramping up its 14nm finFET process by the fourth quarter of 2013.

Some chipmakers have been openly critical about the 20nm foundry planar process, saying the technology puts the industry behind the traditional performance curve. “I know some customers want more,” acknowledged Morris Chang, chairman and chief executive of TSMC, in a recent conference call.

So, at 20nm and beyond, chipmakers are weighing their options and exploring the trade-offs. “There will be customers that will skip 20nm to get to (finFETs),” Chang said. “I think there will be customers that will be light on one (process technology) and heavy on another.”

The benefits of finFETs are clear, but the industry is finally coming to grips with the challenges associated with the transistor technology. Cost, patterning and variation are just a few of the issues. The complexity will require more and deeper collaboration between foundries and their customers. “The challenge for us is to work across the ecosystem with our partners and have earlier tapeouts that are fully debugged and tested,” said Gregg Bartlett, senior vice president and chief technology officer at GlobalFoundries.

All told, the fabless-foundry model is still alive and well, but the business continues to change. Going forward, leading-edge foundries will offer fewer process derivatives. Customers will have fewer choices. And in the future, expect possibly one foundry to exit from the leading-edge process race, with more consolidation seen on the horizon.

Skipping around the IC world
At one time, most leading-edge chipmakers followed the natural progression of process technology nodes. The dynamics began to change starting around the 90nm node, when chipmakers migrated towards sub-wavelength lithography, low-k, design-for-manufacturing (DFM) and other technologies.

IC design and manufacturing costs began to soar. As the complexity and cost escalated at each process node, it was no longer a clear-cut decision to follow the natural cadence of process nodes. Chipmakers weighed the various technical and economic trade-offs.

Starting at 90nm, node skipping among chipmakers became the rule instead of the exception. For example, Netronome is currently shipping communications processors based on a 65nm process from TSMC. Instead of moving to 40nm or 28nm, Netronome recently decided to make a giant leap from 65nm to Intel’s 22nm finFET foundry technology. The decision, according to Netronome, was based on density, power consumption and cost.

Node skipping is expected to reach new heights at the 20nm planar process. The so-called “time-to-market” IC makers, such as AMD, Altera, Nvidia, Qualcomm, Samsung, and Xilinx, likely will make the traditional progression from 28nm to the 20nm planar node before moving to finFETs.

Many of the so-called fast-followers, such as Broadcom, Freescale, Marvell and LSI, are still on the fence. At a recent event, for example, a Marvell representative questioned the feasibility of the 20nm planar node, saying the technology has a “negative ROI.”

Previously, foundries offered several different process derivatives at a given leading-edge node. But at 20nm, GlobalFoundries, Samsung and TSMC will offer only one leading-edge process, thereby providing customers with fewer choices.

The 20nm planar node also brings some new and challenging technologies to the mix, such as double patterning and the introduction of a third layer of local interconnects called the middle-of-the-line. At 20nm planar, there is a performance boost over 28nm, but the transistor speeds slow down as operating voltage is reduced.

IC makers that moved from 40nm to 28nm have experienced a 35% average increase in speed and a 40% power reduction, said Jack Sun, vice president of R&D and chief technology officer at TSMC. In comparison, IC vendors that will move from 28nm to 20nm planar are expected to see a 15% increase in speed and 20% less power, Sun said.

With that in mind, there is a temptation to skip 20nm and migrate to finFETs. FinFETs take the traditional 2D planar design and turn the conductive channel on its side, resulting in a 3D “fin” structure surrounded by a gate that controls the flow of current.

Compared to 32nm planar, finFET transistors enable a 37% performance increase at low voltages and a power reduction of 50% or more, according to Intel. Intel’s own Tri-Gate transistor enables a steeper sub-threshold slope at around 80 mV/decade or below, compared to 100 mV/decade for leading-edge planar transistors, said Mark Bohr, senior fellow at Intel, at a recent event.

“Vdd scaling has slowed down. Leakage is an issue as geometries shrink,” said Srinivas Nori, director of SoC marketing at GlobalFoundries. “The value (that finFETs) bring is that it enables one to lower the Vdd. Leakage is better controlled. The variation of the Vt is also much better controlled.”

The benefits are easy to grasp, but the hard part is obvious. “If I was a designer, I would be worried,” said Horacio Mendez, executive director of the SOI Industry Consortium, a group that is promoting SOI. “If you go back to the standard way of doing things in bulk, and you want a transistor with a different Vt and that drives a different current, you printed different line widths. You just made a fatter transistor. And you paid a little a bit of a penalty in the capacitance,” Mendez said. “How the heck can do you that in finFETs? It’s impossible. So, to make finFETs, you go in quantum steps. The way you actually do this is that you put down one fin, two fins or three fins on a structure.”

Besides the quantum issues, there are other problems. “The fin height is now a huge variable. In a junction-isolated fin, I don’t know how that is accurately controlled. So, from my perspective, this is a tricky thing for an SoC guy to get around. I would imagine you would need pretty stiff design rules to account for this,” he said.

Because of fin height variability, there are fears that the foundries could struggle making bulk finFETs with any consistency. The SOI proponents are pushing fully-depleted SOI (FD-SOI), claiming the technology can reduce the process steps and variability with little or no cost penalty.

New roadmaps
The foundries are still pushing bulk, but they have changed their roadmaps. In September, GlobalFoundries rolled out its finFET technology, dubbed 14nm-XM, based on a “modular fin” approach. GlobalFoundries opted to marry a 14nm front-end fin with a 20nm planar BEOL flow. In doing so, the company has accelerated its finFET process by a year. Product tape-outs are expected in 2013, with production slated for 2014.

“Today, customers, IP vendors and the whole ecosystem can actually start working on finFETs,” said Subramani Kengeri, head of advanced technology architecture at GlobalFoundries. “There are about 7,000 design rules that will carry over from 20nm planar to finFET. From a design point of view, the very early PDKs are almost the same as 20nm.”

Earlier this year, TSMC thought 20nm planar would become a popular node and announced a 20nm pilot line to prepare for the big ramp. But initial 20nm demand is lukewarm. TSMC claims to have 50 tape-outs for the technology, roughly one-fifth compared to that of 28nm.

TSMC’s 20nm pilot line is still on track for 2013. But last month TSMC accelerated its finFET risk production schedule from February 2014 to November 2013. Mass production is slated a year after its 20nm planar process. “This is a somewhat faster cadence than the previous generation,” TSMC’s Chang said.

Meanwhile, UMC said it has developed 20nm planar capability, but the company is not pursuing it as a mainstream process offering. Instead, it is more or less skipping 20nm and pursing finFETs. “After 28nm, finFET will be our focus,” said Shih-Wei Sun, chief executive of UMC, during a recent conference call.