Optimizing DFT With AI And BiST

Experts at the Table: Semiconductor Engineering sat down to explore how AI impacts design for testability, with Jeorge Hurtarte, senior director of product marketing in the Semiconductor Test Group at Teradyne; Sri Ganta, director of test products at Synopsys; Dave Armstrong, principal test strategist at Advantest; and Lee Harrison, director of Tessent automotive IC solutions at Siemens EDA. What follows are excerpts of that conversation. To view part one of this discussion, click here.

L-R: Teradyne’s Hurtarte; Synopsys’ Ganta; Advantest’s Armstrong; Siemens EDA’s Harrison.

SE: How is AI and machine learning changing strategies for DFT?

Harrison: With the introduction of smart technologies that optimize DFT architecture, users now have many options to find the best solution. The easiest way to get there is to let AI drive the process. Everyone is looking at how AI can analyze designs, consider past work, and suggest how to build the DFT architecture. By understanding the tools’ capabilities and feeding that into the AI model, it adapts to what ATPG engineers prefer. This allows the AI to generate an initial DFT architecture. We may never let AI do everything, but it can guide us in the right direction, speeding up design and implementation. There are so many factors to consider now in building the best DFT solutions. It’s like having 1,000 LEGO bricks and trying to build the best possible structure. AI guidance is essential for navigating all the options.

Hurtarte: Regarding the IEEE standard, specifically IJTAG, you now can bypass specific IP blocks. It’s like a door. If you know there are no problems with the door, you don’t test it. In a chip with many IP blocks, you can test all the blocks, or you can learn over time which blocks never fail as you test the wafer,. You might even learn patterns for specific wafers or die within the wafer. This allows you to use AI to train the tester to focus on where you get the most value, reducing test time and optimizing efficiency.

Ganta: AI is playing a significant role in optimizing DFT by addressing challenges at both the structural and architectural levels. ATPG pattern generation, which accounts for a substantial portion of test time in structural tests, is a key area of focus. Saving even a millisecond or microsecond in high-volume manufacturing can result in significant cost reductions. AI-driven tools are being developed to streamline this process by automating optimization. For example, AI can analyze designs and explore different parameter combinations to deliver optimal pattern count reduction while maintaining test coverage and minimizing the need for manual adjustments. Additionally, AI is being used to optimize DFT configurations such as the number and length of scan chains or the type of compression logic employed. This allows for more efficient use of resources, ultimately reducing both test time and cost. The ability to leverage AI in this way is becoming increasingly important as designs grow in complexity and the demand for faster, more cost-effective testing continues to rise.

Armstrong: One challenge test engineers face is the sheer volume of pattern content. In the past, a large device might have had 20,000 pattern segments generated by the structural test itself. Now it’s common to see over 100,000 patterns. AI can help sort through all those patterns for the best value with the least amount of over-testing.

SE: How important is the collaboration between the design and the test teams for optimizing DFT?

Hurtarte: During the design phase, designers know which specific IP blocks within the chip were the most challenging in terms of things like timing closure, signal integrity, and noise isolation. They know the challenges from timing closure, DRC checks, etc. If we can get that information into the test environment, we can look for those areas that have a higher probability of failure because of the design characterization. That would be significant collaboration with the test side.

Ganta: Collaboration needs to extend beyond just the design or RTL teams. It must encompass the entire RTL-to-GDS flow. DFT, like functional design, goes through verification, static timing analysis, and timing closure, making it essential to collaborate across these stages. Equally important is ensuring that the tools used in this flow are well-integrated to support DFT seamlessly. For example, power budgeting during structural testing requires accurate insights into sequential logic, combinational logic, and memories. Tools that allow for precise targeting of ATPG patterns can help ensure the process is right the first time when silicon is manufactured. Similarly, optimizing compression, scan chains, and placement with minimal impact on performance, power, and area (PPA) is critical to achieving effective DFT integration across the flow. This approach, which integrates DFT into all stages of the RTL-to-GDS process, enables better collaboration and ensures that test strategies align with the broader design and implementation objectives.

Armstrong: To have collaboration, you have to speak the same language. Functional test content inclusion allows test and design to finally talk the same language. They do the simulations of the functional test. That’s what they care deeply about. I would call mission mode, or functional testing, the enabler for true collaboration moving forward.

Harrison: I remember when design engineers would do the DFT implementation, throw it over the wall to the back-end guys, and then throw that over the wall again to the product engineers. There was no discussion or communication between any of those teams. Now, you’re seeing data being collected at all stages throughout the process, from the architecture and design stages, as the device moves through build-up to manufacturing test, then through volume test, and then you’ve got all of the data coming through. There’s a huge desire now to collect data at all of these different levels. Having all that data is great, but as Dave said, if you don’t speak the same language it’s only useful in isolated ways. Striving toward an implementation where all of that data can be cross-referenced and queried in the same way is vitally important. If you find anomalies in the test data, you have the ability to query that and trace it back to the design and implementation to understand the root cause. Having all this data intertwined in the same supported structure is absolutely critical to making the whole thing work.

SE: How do you handle the limitations of built-in self-test techniques when you get into more complex and high-performance ICs, and how do you see that evolving to better support DFT?

Ganta: Built-in self-test (BiST) is gaining prominence, particularly in automotive and data center applications, where in-field or in-system testing is increasingly necessary. One of the main challenges with logic BiST is its reliance on a single seed, which makes achieving the desired test coverage difficult, especially in designs with a significant amount of random-resistant logic and presence of unknowns (X). One approach to address this uses multiple deterministic seeds and built-in X-tolerance as part of the compression architecture. Another challenge is to be able to use the same compression architecture for manufacturing test and in-system test to minimize additional area overhead, as well as validation effort. The ideal solution would have the same compression logic being configured for a complete end-to-end test solution, including ATE, burn-in, system-level test (SLT), and in-system and in-field test applications. Memory BiST also presents unique challenges, as memories now constitute more than 50% of the die and have extremely high densities. To address new technology nodes, memory BiST algorithms need continuous refinement and adaptation to keep pace with evolving requirements. This involves a combination of generating test chips, characterizing new memory technologies, and fine-tuning the algorithms to foresee and address future needs effectively.

Armstrong: The complex parts we’re handling today tend to be training AI engines and inference engines. A convolutional neural network typically needs two things to do anything, including BiST testing — an array of coefficients, and an input data array. One of the things we need to do is provide an effective way to enable BiST by giving it a deterministic set of input criteria, and that could be memory scan-in for various coefficients, for example.

Harrison: Logic-based and memory-based BiST is widely used, particularly in automotive safety applications, but there is a growing need for higher-quality testing systems that can support evolving requirements. One area of advancement is in-system deterministic test patterns, which allow for re-using test pattern content originally developed for automated test equipment (ATE) and applying it directly in-system. This enables comprehensive diagnosis and testing without the need for physically removing components, which is particularly useful in environments like data centers. For instance, when a part of a data center experiences failure, traditional methods often require removing the board, shipping it back to a factory, and carefully unsoldering the device for testing. That process is fraught with risks and inefficiencies. With in-system deterministic testing, a full set of manufacturing test patterns can be applied directly in-system, enabling detailed diagnosis and failure analysis without physically removing the hardware. This approach significantly streamlines the process and reduces downtime. Another advantage of this method is the ability to adapt test patterns over time. As products evolve and new faults are discovered, test content can be updated to address these changes, ensuring that test patterns remain optimized and maintain high quality throughout the product lifecycle.

Hurtarte: There will always be limitations in testing methodologies, but continuous innovation allows us to address these challenges effectively. The key lies in managing the capabilities of today’s tools while preparing for future needs. A significant approach involves shift-left and shift-right strategies, along with real-time data sharing between wafer probe and upstream processes. Real-time, bi-directional data streams enable informed decisions at every stage of the testing process. For example, machine learning solutions can analyze test data and help optimize the test flow dynamically. By incorporating system-level test, automated test equipment (ATE), or wafer probe where appropriate, we can identify and compensate for existing limitations. Real-time collaboration across these stages ensures that failures are detected efficiently and that test processes remain flexible and adaptive. Ultimately, integrating advanced data analytics and fostering collaboration across the test flow are critical strategies for overcoming the inherent limitations of current testing frameworks. These approaches support better optimization and allow for greater adaptability as devices and test environments grow increasingly complex.

SE: What’s most important for your customers to understand about DFT?

Armstrong: The foundational principles of observability and controllability remain critical to effective test strategies. As designs grow more complex, the depth of logic makes it increasingly challenging to access and test specific elements, such as a single flip-flop buried many stages deep in the design. This understanding is essential because it influences key decisions about partitioning, test design, and where to insert built-in self-test structures. Beyond insertion, the scheduling of BiST tests versus structural tests introduces additional challenges. For example, thermal implications must be carefully managed, as one type of test can impact the conditions under which another is executed. The integration and interaction of these elements must be thoughtfully planned to ensure accurate results without unintended consequences. Emerging technologies like scan networks are becoming indispensable. To fully leverage their potential, it’s important to understand how to integrate them effectively into the overall testing strategy. These advancements highlight the importance of a comprehensive approach to observability and controllability, ensuring that all aspects of a design are thoroughly tested in a scalable and efficient manner.

Harrison: With the diverse range of technologies available today, it’s critical to emphasize the importance of architecting flexibility into designs early on. While it’s not always feasible to achieve a fully optimized architecture from the start, incorporating enough configurability allows for adjustments once silicon is available and patterns are being tested. For example, in testing multiple cores, achieving the right balance between power optimization and test time is crucial. Adjusting the number of cores tested in parallel involves tradeoffs. Testing too many cores simultaneously can lead to power issues, potentially causing higher fallout rates, while testing fewer cores might prolong test times. The goal is to find the optimal balance between pushing the DFT network’s capabilities and achieving acceptable yields. A rigid upfront architecture risks being either power-inefficient or time-intensive when it comes to testing. By building in flexibility, teams can fine-tune parameters, such as core groupings and power distributions, later in the process. This adaptability can significantly impact overall cost savings and yield optimization, making it a vital consideration during the architectural phase.

Hurtarte: DFT is just one part of a broader equation. Fault coverage and cost of quality are multi-variable problems that require a comprehensive approach. DFT plays a critical role, but it must be combined with other strategies, such as ATE, system-level test, and mission mode testing, to achieve optimal results. To truly optimize cost and fault coverage, each chip requires a case-by-case analysis. There is no universal solution. High-performance computing, RF, and optical devices, for example, often demand different testing approaches. While DFT can address a significant portion of potential faults, it cannot catch everything. Additional test insertions are necessary. For instance, with ATE there is a limit to what can be achieved. Increasing test time may yield diminishing returns and become cost-prohibitive. At that point, shifting to mission mode or system-level test can uncover the next layer of issues. Each step in the test flow must be carefully analyzed and tailored to the specific chip’s requirements to ensure efficient fault detection and cost management. A systematic, chip-specific analysis allows for crafting the most effective test strategy, leveraging DFT in combination with other methodologies to address the unique challenges of each design.

Ganta: The ultimate goal is to reduce test costs, which continue to grow exponentially. Achieving this requires adopting advanced technologies and rethinking traditional approaches. This shift isn’t without its challenges. It requires changes in mindset and methodology to fully leverage these innovations. For example, advanced flows like packetized scan methods offer significant benefits for optimizing bandwidth and efficiency. Unlike static pin configurations, packetized scans utilize time-multiplexed approaches to run multiple cores simultaneously, which maximizes resource utilization. However, implementing these techniques requires robust ecosystem support, including seamless collaboration with test equipment providers and effective debugging strategies to address the complexities of time-multiplexed systems. AI, machine learning, and data analytics also present emerging opportunities to further optimize silicon testing. These technologies enable smarter test strategies by analyzing data patterns, predicting issues, and optimizing the testing process dynamically. By integrating such tools into the test flow, companies can achieve substantial cost and time savings while maintaining high fault coverage.

SE: Are there any other considerations we need to take note of?

Harrison: One of the significant topics being discussed right now is power — specifically, its impact on DFT architecture and testing methodologies. Engineers increasingly are focused on understanding power distribution not just at the chip level, but also at the core level, identifying potential hot spots across the die. For instance, if you isolate a few cores in one corner of the die and test them in isolation, you may push the device power to its maximum limit for testing. However, this can overstress that specific area, leading to localized power issues and potentially lower yield. To mitigate this, testing strategies need to account for the overall spread of power across the device, balancing the power requirements without overstressing any particular area. Historically, power analysis during testing involved rough calculations at the chip level, which informed the design of power grids and ATE boards. Today, the focus has shifted toward far more granular power reporting and control. Engineers are now seeking insights at the block level and even at the pattern level, asking questions like, “which pattern generates the highest peak power?” This shift is driving a demand for more detailed power analysis and control mechanisms to optimize the testing process and improve device reliability. Managing these power challenges is becoming a critical aspect of modern DFT strategies.

Hurtarte: In the context of heterogeneous integration and advanced packaging, the industry still lacks a comprehensive tool that models the entire flow — from wafer processing and stack assembly to testing, packaging yields, and logistics. Such a tool could provide a unified view, enabling optimization of the entire stack, assembly, and test strategy. This is particularly important as chip complexity and diversity continue to grow, requiring tailored approaches for different types of designs. The challenge lies in addressing the unique needs of each application, as no single solution fits all. As we advance into chiplets and heterogeneous integration, even with robust DFT methods, the absence of a holistic modeling system remains a significant gap. Developing this capability is an area where further innovation is needed to better align test strategies with the complexities of advanced packaging.

Ganta: One important point is that, when discussing quality, the focus often skews heavily toward digital, while the analog and mixed-signal portions of the die tend to be overlooked. This raises a critical question. What is the actual fault coverage achieved in analog or mixed-signal testing? The digital side benefits from well-established fault grading methodologies, where coverage metrics like stuck-at or transition delay faults can be quantified precisely. However, similar rigor has not been consistently applied to analog fault grading. A step forward in addressing this gap is the new IEEE standard, P2427, which defines how to grade analog fault models based on tests. This is crucial because, historically, analog testing has often relied on qualitative assessments rather than measurable fault grading. For the industry to improve in this area, there needs to be more focus on developing robust grading methodologies for analog and mixed-signal circuits, similar to what exists on the digital side. Standards like P2427 provide a foundation to ensure that analog tests are not only effective but also quantifiable, driving a more comprehensive approach to overall die quality.

Armstrong: The design of modern devices is significantly influenced by the replication, or ‘copy-pasting,’ of cores. This includes multiple cores on a single piece of silicon, or multiple pieces of silicon on an interposer. While duplicating cores in the design phase is relatively straightforward, replicating the corresponding test content is far more complex. Efforts are underway — such as those by IEEE committees — to streamline this process, but we still lack comprehensive solutions that can seamlessly generate test patterns for replicated cores. A good analogy would be assembling a set of modular building blocks, where each type of core corresponds to a distinct ‘color’ of block. Ideally, we should be able to generate test patterns automatically for each configuration. At ITC, there was a detailed discussion on how different components are integrated, but everyone acknowledged the significant challenge of creating effective tests for the resulting diverse configurations. This highlights an area where more work is needed, particularly in end-to-end cost optimization, which ties together assembly, manufacturing, and test. Developing tools that can address these challenges holistically is not easy, as I’ve learned through my own attempts at tackling this issue. However, advancing in this direction would offer significant benefits for the industry by improving efficiency and reducing costs across the entire process flow.