Overcoming The Growing Challenge Of Dynamic IR-Drop

IR-drop has always been somewhat of an issue in chip design; voltage decreases as current travels along any path with any resistance. Ohm’s Law is likely the first thing that every electrical engineer learns. But the challenges related to IR-drop (sometimes called voltage drop) have increased considerably in recent years, especially the dynamic IR-drop in the power/ground grid as circuits switch. As wires get smaller and closer, and layouts get denser, dynamic IR-drop becomes a bigger factor. This is especially true for advanced process nodes of 3nm and smaller. Issues become more serious as chip frequency and power consumption increase, so dynamic IR-drop continues to grow with each new generation of silicon.

When the voltage supplied to a logic cell decreases, that changes its delay. This can result in violations of setup and hold timing and introduce noise in the power supply nets from the on-chip power/ground grid. Timing violations can result in costly down-binning during chip test, degrade performance in the field, or even cause a chip to stop operating properly. To minimize this degradation, design engineers strive to reduce dynamic IR-drop as much as possible. Unfortunately, it has been difficult to diagnose the root causes for dynamic IR-drop and they are time-consuming to fix.

In the traditional flow, after the design has been placed and routed, resistance and capacitance (RC) values are extracted from the layout. During design signoff, power integrity analysis and fixing are available in the physical design step to help block-level and top-level engineers converge. The engineers perform post-layout static timing analysis (STA) and feed the results into an IR-drop analysis engine.

Fixing any dynamic IR-drop issues requires making an engineering change order (ECO) to the design and starting the four-step process again. This is a manual effort that may require multiple iterations though the layout-extraction-STA-analysis loop.

This flow has several fundamental weaknesses. The layout process has no awareness of IR and so cannot takes steps to minimize IR-drop. Timing and IR analysis are not available within a single tool, increasing the turnaround time (TAT) for each iteration. Further, some potential solutions, such as strengthening the on chip power/ground grid, may not be feasible in the limited time period available for a manual ECO. The upshot of this disjointed flow is that each dynamic IR-drop ECO is a costly manual effort, delaying the time to finalize the design and achieve IR-aware signoff. “Over-fixing” dynamic IR-drop issues might reduce iterations but will yield suboptimal power-performance-area (PPA) tradeoffs.

There is only one way to resolve this dilemma: an automated signoff timing-aware dynamic IR-drop ECO process for the early and late stages of the design flow. IR signoff must be natively integrated within the place and route stage, so the layout-analysis loops happen automatically within a single tool. Elimination of manual iterations and long TAT “shifts left” the IR signoff process and shortens time to market. Power, signoff IR-drop, and signoff timing are all analyzed concurrently, leveraging cloud computing and massive parallelism to reduce runtime, where needed. Finally, a late-stage signoff timing aware IR-ECO solution is important for last-mile design closure. The resulting power integrity design flow has several key capabilities:

• Dynamic power shaping
  • Staggers timing of registers that switch simultaneously
  • Focuses on real issues with IR-drop signoff accuracy
• IR-driven placement
  • Avoids surprises found late in the traditional manual loop
• IR-driven concurrent clock and data (CCD) analysis
  • Uses machine learning (ML) for 10x faster prediction
• IR-driven power/ground grid augmentation
  • Performs parallel multi-scenario analysis and optimization
  • Enables improvements impossible in the traditional manual flow
• IR-aware signoff timing (STA)
  • Understand sensitivity of design blocks toward IR-drop from power grid designs
  • Use as last-mile waiver for IR-drop violations based on signoff timing slack
  • Minimize IR and timing pessimism, avoid over-fixing
  • Perform timing-ECO to fix IR-drop violations to improve the design closure
• IR-driven signoff ECO
  • Smart methods for identification of dynamic IR-drop root causes
  • Automatic fixes for dynamic IR-drop effects based on smart IR profiling without impacting timing

This integrated flow provides a complete solution for layout, STA, IR-drop analysis and optimization, and ECOs to fix any issues. Just such a solution is available within the Synopsys Fusion Design Platform, a RTL-to-GDSII solution enabling a highly convergent, full-flow digital implementation. Synopsys Fusion Compiler and IC Compiler II provide a production-proven solution for physical implementation. Tweaker ECO is integrated into the platform for automated fixes, including for dynamic IR-drop issues. The solution also includes the Synopsys PrimeTime static timing analysis tool for trusted signoff and the PrimeShield solution for design robustness analysis and optimization at advanced nodes.

In summary, dynamic IR-drop analysis is a growing problem as geometries shrink and clock rates increase. The traditional manual flow takes multiple iterations and impacts time to market. An integrated, automated flow reduces development time and saves precious engineering resources, leading to more robust designs. The resulting chip has better PPA, with greater performance and lower peak and average power consumption, yielding a more successful product earlier in the market window.

We will be highlighting this and many other related topics in the signoff and digital implementation tracks at SNUG Silicon Valley 2022, which will be held virtually on March 30-31 and then available on-demand through July 2022. For more information on the Fusion Design Platform, please visit our website.