Packaging Tradeoffs More Complex Than Ever

By Ann Steffora Mutschler
Driven by high-speed interfaces, the demand for TSVs and the complexities that new process nodes bring, older packaging technologies like wirebonding can’t keep up.

The latest and greatest flip chip technologies offer much more flexibility, but at a cost. As such, the package plays a larger role than ever in determining system specifications because, depending on the packaging technology used, certain system parameters are either limited or not. For these reasons packaging is being considered up front in the design process—even at the very earliest planning stages. Moreover, the cost of packaging comprises a non-trivial portion of the total system cost. Throw 2.5D and 3D ICs into the mix and things get really interesting.

These issues are breaking down the brick walls between the IC designer and the packaging designer, observed Brad Griffin, product marketing director for Cadence’s Allegro product line. “I think we have hit a point where if you don’t at least consider some of the aspects simultaneously you’re going to end up with a system that either doesn’t perform like you would like it to or has additional cost than you would like it to have.”

Shafy Eltoukhy, vice president of manufacturing operations at Open-Silicon, agrees. “Essentially when we talk to the customer initially we try to understand from them what their thermal requirements are, like power, the footprint of the package, the thickness of the package and the cost. Also, if it’s a consumer part it will be different than if it’s a networking part. The cost has a big impact on the selling price. There are a lot of factors that come in at the very beginning, that being the power dissipation, signal integrity, form factor of the package and so on.”

There’s a complicated matrix to designing a package. “In some cases, at the very beginning, you don’t know exactly what the die size is going to be because customers keep adding functions and the die size keeps changing in the early stage. Having all the requirements from the mechanical to power to this and that, as well as the layout or the floorplan of the die, is also changing up front. The package has to be part of the very early stage of the design,” he said.

The company ties the package to the floor planning and the requirement as far as the speed and other considerations. Package design engineers get on board very early in the process—even before designing the die itself—to look at it from the floor planning point of view. That includes where to put high-speed interfaces, how fast these are going to be, packaging technology, i.e. flip chip or wirebond, power expectations, and so on. “It’s very complicated and people have started putting a very good interface between the packaging and floor planning engineers,” Eltoukhy added.

Broadcom recently detailed its experience making early tradeoffs during Cadence’s CDN Live event in March. The presentation can be viewed here (registration required).

In this case, using Cadence technology under development, Broadcom enabled its PCB designer to look at what the package footprint should be to best match the components on the board. From there it drives up from the package footprint to the bump matrix for the chip. They were able to determine the ideal bump matrix for the chip to be able to match the package footprint. Then from the bump matrix that drove the I/O pad ring to get the I/Os and chips placed properly.

Then, when it comes to 2.5D design, packaging issues are actually more complex than what they will be with true 3D ICs, according to John Park, methodology architect for IC packaging and pathfinding technologies in the Systems Design Division of Mentor Graphics. “I believe—and many of my customers believe—it is more complex because you have this intermediate substrate in which the die connect through these small microbumps, and there’s this die-to-die connectivity that happens on some unknown number.”

Engineering teams really want to save costs, or at least make the tradeoff of cost and thermal, etc., Park added. “They want some global routing technology that allows them to say, ‘What if, on the interposer, I limit it to three metal layers? Does that mean I need to add two more layers to my package substrate or does it mean that I have to add eight more layers to my package substrate?’ In that case, maybe they say, ‘I’m going to add one more metal layer to my silicon interposer so that I can reduce the layer count of the package.’ Now the costing gets very complex because you have this new intermediate routing structure that sits in between the traditional die to package connectivity that greatly impacts cost, routability, signal quality—all these types of things.”

Although some of these issues won’t be a problem with 3D, don’t expect a mass exodus from 2.5D when 3D becomes mainstream because it may be more expensive, noted Cadence’s Griffin. “You’re going to have to get to a certain quantity before you’re going to realize the value in going to 3D IC, so there’s going to be still a fair amount of chips in the lower to mid quantities for which they want to realize the performance gains of going to a silicon substrate to connect things together but they can’t necessarily go to the expensive TSMC to be able to connect all these things together properly. [Systems companies] will rely on less-expensive silicon interposer technology; it will have a little less performance but cost-wise, it will just be more efficient for them. I think you’re going to see both for quite some time, but i think you’re going to see the very-high-quantity things move to 3D IC as much as possible.”