tag: Synopsys

Dealing With Sub-Threshold Variation
By Bryon Moyer - 12 Nov, 2020 - Comments: 0

Chipmakers are pushing into sub-threshold operation in an effort to prolong battery life and reduce energy costs, adding a whole new set of challenges for design teams. While process and environmental variation long have been concerns for advanced silicon process nodes, most designs operate in the standard “super-threshold” regime. Sub-threshold designs, in contrast, have unique variatio... » read more

Difficult Memory Choices In AI Systems
By Ann Mutschler - 12 Nov, 2020 - Comments: 0

The number of memory choices and architectures is exploding, driven by the rapid evolution in AI and machine learning chips being designed for a wide range of very different end markets and systems. Models for some of these systems can range in size from 10 billion to 100 billion parameters, and they can vary greatly from one chip or application to the next. Neural network training and infer... » read more

Blog Review: Nov. 11
By Jesse Allen - 11 Nov, 2020 - Comments: 0

Mentor's Chris Spear proposes mixing together the compactness of the field macro style with the preciseness of the do methods when writing a UVM transaction class. Cadence's Paul McLellan looks back at the history of EPROM, some of the difficulty with actually erasing it, and the subsequent development of EEPROM. Synopsys' Tuomo Untinen explains three WPA2 authentication vulnerabilities r... » read more

Making IC Test Faster And More Accessible: Part 2
By Randy Fish - 11 Nov, 2020 - Comments: 0

Recently, my colleague Robert Ruiz described a new approach to scan test that utilizes the high-speed I/O (HSIO) ports that exist on most chips. The benefits of this new approach include reduced test time and cost thanks to the high-speed interface. Simplified pin electronics and tester setup are also benefits, as is the ability to run manufacturing tests in the field in support of silicon life... » read more

Lower Process Nodes Drive Timing Signoff Software Evolution
By Synopsys - 10 Nov, 2020 - Comments: 0

A dramatic rise in design complexity has led to a slew of new signoff challenges that impact the ability to predictably meet PPA targets. Smaller technology nodes and larger design sizes have caused the number of corners and modes to grow exponentially leading to much longer turnaround times for timing signoff. Moreover, larger design sizes demand huge compute resources for timing signoff. I... » read more

Adaptive Test Gains Ground
By Anne Meixner - 10 Nov, 2020 - Comments: 0

Not all devices get tested the same way anymore, and that’s a good thing. Quality, test costs, and yield have motivated product engineers to adopt test processes that fall under the umbrella of adaptive test, which uses test data to modify a subsequent test process. But to execute such techniques requires logistics that support analysis of data, as well as enabling changes to a test based ... » read more

Does HW Vs. SW Choice Affect Quality And Reliability?
By Bryon Moyer - 10 Nov, 2020 - Comments: 0

Electronic systems comprise both hardware and software. Which functions are implemented with hardware and which with software are decisions made based upon a wide variety of considerations, including concerns about quality and reliability. Hardware may intrinsically provide for higher device quality, but it is also the source of reliability concerns. This is in contrast with popular views of... » read more

The Challenge Of Balancing Performance And Accuracy For Advanced Node Timing Signoff
By Rahul Deokar - 10 Nov, 2020 - Comments: 0

As process nodes shrink, complexity, cost and overall risk expand. Process variability that once was once acceptable now becomes a critical item as operating voltage decreases. Simply adding design margin makes the chip non-competitive. Physical effects that were once ignored now become critical as well. The impact of interconnect can no longer be modeled based on simple circuit topology. Layou... » read more

Comprehensive Simulation Of Power Electronics Systems
By Synopsys - 09 Nov, 2020 - Comments: 0

Power electronics systems are at the heart of many important and growing industries, from all-electric vehicles to renewable energy generation. Optimizing the design of these systems requires accurate modeling and simulation long before construction of physical prototypes. SPICE-level simulation has been the traditional solution and, while it still plays a key role, it cannot satisfy all requir... » read more

Growing Complexity Adds To Auto IC Safety Challenges
By Ann Mutschler - 05 Nov, 2020 - Comments: 0

The automotive industry is working to streamline, automate and tame verification of automotive electronic control units, SoCs and other chips used in vehicles, many of which are becoming so complex and intertwined that progress is getting bogged down. Modern cars may have up to 100 ECUs, which control such vehicle functions as engine, powertrain, transmission, brakes, suspension, entertainme... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy