tag: Cadence

5nm Design Progress
By Ann Mutschler - 17 Jul, 2018 - Comments: 1

Activity surrounding the 5nm manufacturing process node is quickly ramping, creating a better picture of the myriad and increasingly complex design issues that must be overcome. Progress at each new node after 28nm has required an increasingly tight partnership between the foundries, which are developing new processes and rule decks, along with EDA and IP vendors, which are adding tools, met... » read more

Architecting For AI
By Ann Mutschler - 17 Jul, 2018 - Comments: 0

Semiconductor Engineering sat down to talk about what is needed today to enable artificial intelligence training and inferencing with Manoj Roge, vice president, strategic planning at Achronix; Ty Garibay, CTO at Arteris IP; Chris Rowen, CEO of Babblelabs; David White, distinguished engineer at Cadence; Cheng Wang, senior VP engineering at Flex Logix; and Raik Brinkmann, president and CEO of O... » read more

Cadence Cloud—The Future Of Electronic Design Automation
By Cadence - 16 Jul, 2018 - Comments: 0

Design complexity and competitive pressures are driving electronics developers to seek innovative solutions to gain competitive advantage. A key area of investigation is applying the power of the cloud to electronic design automation (EDA) to dramatically boost productivity. Grounded in its long history of providing hosted design solutions (HDS) and internal experience with cloud-based design, ... » read more

Verification As A Flow (Part 2)
By Brian Bailey - 11 Jul, 2018 - Comments: 0

Semiconductor Engineering sat down to discuss the transformation of verification from a tool to a flow with Vladislav Palfy, global manager application engineering for OneSpin Solutions; Dave Kelf, chief marketing officer for Breker Verification Systems; Mark Olen, product marketing group manager for Mentor, A Siemens Business; Larry Melling, product management director, System & Verificati... » read more

Blog Review: July 11
By Jesse Allen - 11 Jul, 2018 - Comments: 0

Synopsys' Taylor Armerding warns that while significant router vulnerabilities have been known about for years, security mostly hasn't been getting better, leading to a 539% increase in attacks targeting routers since the fourth quarter of 2017. In a video, Mentor's Colin Walls walks through how to deal with the initialization of non-volatile RAM in embedded programming, including suggestion... » read more

Week In Review: Design, Low Power
By Jesse Allen - 06 Jul, 2018 - Comments: 0

CAST debuted an IP subsystem implementing the latest IEEE standards for Time Sensitive Networking (TSN) over Ethernet. The TSN_CTRL Subsystem combines three IP cores, a time synchronizer, traffic shaper, and Ethernet MAC. It implements a hardware subsystem that operates without software assistance once programmed. The IP communicates timing information to the system, and allows the system to de... » read more

Design Reuse Vs. Abstraction
By Ann Mutschler - 05 Jul, 2018 - Comments: 1

Chip designers have been constantly searching for a hardware description language abstraction level higher than RTL for a few decades. But not everyone is moving in that direction, and there appear to be enough options available through design reuse to forestall that shift for many chipmakers. Pushing to new levels of abstraction is frequent topic of discussion in the design world, particula... » read more

Verification As A Flow (Part 1)
By Brian Bailey - 05 Jul, 2018 - Comments: 2

Semiconductor Engineering sat down to discuss the transformation of verification from a tool to a flow with Vladislav Palfy, global manager application engineering for OneSpin Solutions; Dave Kelf, chief marketing officer for Breker Verification Systems; Mark Olen, product marketing group manager for Mentor, A Siemens Business; Larry Melling, product management director, System & Verificati... » read more

Blog Review: July 4
By Jesse Allen - 04 Jul, 2018 - Comments: 0

Applied Materials' Sundeep Bajikar argues that to get the full benefits of AI, new computing architectures are needed – and that will require new breakthroughs in materials engineering to get beyond classic 2D scaling. Cadence's Tom Wong considers to what extent chip dis-integration is happening and how the industry can cope with the escalating costs of new process nodes and higher-speed i... » read more

The Darker Side Of Consolidation
By Ed Sperling - 02 Jul, 2018 - Comments: 1

Another wave of consolidation is underway in the semiconductor industry, setting the stage for some high-stakes competitive battles over market turf and sowing confusion across the supply chain about continued support throughout a product's projected lifetime. The consolidation comes as chipmakers already are grappling with rising complexity, the loss of a roadmap for future designs as Moore... » read more

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