tag: Synopsys

Rethinking Test
By Ann Mutschler - 11 Feb, 2010 - Comments: 0

By Ann Steffora Mutschler The responsibility of semiconductor test has long sat solely with the test engineer as the chip designer focused on the functionality of the device. However, particularly in low-power designs, when the device is being tested, much higher power levels are applied than normal functional operation – sometimes causing the device to fail. This ‘false failure’ c... » read more

Expert Shootout: Parasitic Extraction
By Ed Sperling - 11 Feb, 2010 - Comments: 0

By Ed Sperling Low-Power Engineering sat down to discuss parasitic extraction with Robert Hoogenstryd, director of marketing for design analysis and signoff at Synopsys, and Carey Robertson, product marketing director for Calibre Design Solutions at Mentor Graphics. What follows are excerpts of that conversation. LPE: As we move into 32/28nm, are the parasitics getting worse and is it gett... » read more

Low-Power And RF Design Heighten Signal-Integrity Concerns
By Various Writers - 28 Jan, 2010 - Comments: 0

By Ellen Konieczny As active devices and interconnect wires shrink and are placed closer together with the march of Moore’s Law, signal integrity is becoming a huge concern. If it is not maintained, a design’s future may be marred by lower yields, unreliable performance, and failure to work efficiently—if at all. For low-power and radio-frequency (RF) designs, which are being prod... » read more

Should Sign-Off And Implementation Be Separate Tools?
By Ann Mutschler - 28 Jan, 2010 - Comments: 0

By Ann Steffora Mutschler In the last stages of design, how data is readied for manufacturing used to be relatively straightforward. Point tools were used to implement the design via a place and route tool then the design was “signed off” with physical verification software. Sign-off is the gate the design goes through before it can go into manufacturing. The design must meet the qua... » read more

Remaking The Design Landscape
By Ed Sperling - 28 Jan, 2010 - Comments: 0

By Ed Sperling Every now and then a new trend comes along in the semiconductor design world, often because an old tool doesn’t work well anymore or because a new one is achieving critical mass. Lithography moved to immersion when the wavelength couldn’t be refracted far enough anymore. Designers at the advanced end of Moore’s Law began using tools like high-level synthesis and Transa... » read more

Value Shift
By Ed Sperling - 27 Jan, 2010 - Comments: 0

System Level Design talks with Tom Quan of TSMC, John Koeter of Synopsys, Kalar Rajendiran of eSilicon and Phil Yastrow of Avago about where the value has shifted in the semiconductor design chain and why. [youtube vid=MvSaHSYDqVQ] » read more

Journey To The Center Of The Ecosystem
By Ed Sperling - 14 Jan, 2010 - Comments: 0

From the outside it looks like business as usual, but the race for board seats on the GSA has become particularly competitive this year. GSA originally was created as an organization for fabless companies, but you wouldn’t know that looking at its membership roster. It has evolved into a who’s who of the entire semiconductor supply chain, including everyone from foundries like TSMC and... » read more

Verifying Low-Power Designs
By Ed Sperling - 14 Jan, 2010 - Comments: 0

By Ed Sperling Power islands and multiple voltages used to be reserved for cell phone and process companies, but as more companies move to 65nm and 45nm process nodes these approaches to saving power—particularly in chips with multiple cores—are becoming mainstream. The problem isn’t in the architecture of the chips, although that certainly brings its own set of challenges. More and m... » read more

Combining Power And Synthesis
By Ann Mutschler - 14 Jan, 2010 - Comments: 0

By Ann Steffora Mutschler Each passing design node shrinks electronic designs ever smaller and more complex, which has made power management a critical design priority – even in the synthesis step in the design flow. Synthesis has always been an integral part of the design process, particularly at the RTL level. But as chip design has become more complicated, the need to raise the pro... » read more

Experts At The Table: Rising Complexity Meets Verification
By Ed Sperling - 18 Dec, 2009 - Comments: 0

By Ed Sperling Low-Power Engineering sat down to discuss rising complexity and its effects on verification with Barry Pangrle, solutions architect for low power design and verification at Mentor Graphics; Tom Borgstrom, director of solutions marketing at Synopsys; Lauro Rizzatti, vice president of worldwide marketing at EVE, and Prakash Narain, president and CEO Real Intent. What follows are... » read more

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