Playing With Chip Volumes

The overall market for semiconductors continues to grow, but the number of applications that will generate enormous volumes continues to shrink. In theory, this is good for the overall semiconductor industry, but it raises important questions about where R&D dollars will go in the future.

The fundamental problem is that the semiconductor business is a volume business for one or two markets. Everything about it—from design and IP to processes, yield, test and manufacturing—is all about moving wafers through a fab at the highest speed possible. That provides the necessary economies of scale that have made computers of one sort or another almost ubiquitous.

Consider a 1990 advertisement (Infoworld Aug. 6, 1990, p. 73) for a $3,999 Northgate Computer Systems desktop PC, trumpeting a 33MHz 386 PC with 1Mb of RAM on the motherboard. This is roughly the equivalent of a low-end sensor today, but the sensor includes on-chip memory and I/O and the ASP is less than $10.

There are three major trends underway that could alter this picture going forward, though, with dozens of permutations of each of those trends.

First, and the most obvious, is that the cost of device scaling is rising at each new node, while the market for billions of units of the same device is flattening. Given the fact that it costs $1 billion plus for each new manufacturing process at advanced nodes, plus another $10 billion or so to equip a state-of-the-art fab at 10/7nm, that requires a huge volume of chips to recoup an investment. The problem is that there is no obvious successor to the smart phone, which means the basic strategy here has to change.

Second, the Internet of Things is splintering existing markets and adding some new ones. Several years ago a common assumption was that one chip would serve all needs across multiple markets. That was wishful thinking. An application processor developed for a smart phone cannot be used in a smart watch because the battery isn’t big enough. Each solution for these markets requires a custom, or at least a semi-custom approach. But that doesn’t generate the volume necessary to continue building expensive state-of-the-art fabs. Even those chips that do require advanced processes will likely not require the same volumes as in the past.

And third, the emphasis on advanced packaging is growing. While growth in this market largely has involved chips developed at a single process node, packaged solutions (FO-WLP, 2.5D, SiP) are now under development that involve chips and chiplets developed at multiple process nodes. If this kind of mixed-node packaging grows to what some analysts and industry insiders expect, it could spur volume production at every node, including platform-type CPUs and FPGAs at 7nm, and possibly even at 5nm and 3nm.

This has important implications for semiconductor manufacturing going forward. Scaling isn’t over, but decisions will be much more judicious about what does get scaled. The way forward appears to be a tighter integration of different technologies, regardless of how that is done, rather than trying to integrate everything on a single chip. Building chips at the most advanced nodes only makes sense if it involves those parts of the chips that have an affinity for scaling, meaning digital logic with very regular structures.

But this picture only works if the supply chain restructures to rationally develop pieces that can snap together the way the components did in a 1990s PC. Getting to that point will require standards, an investment in better integration strategies, and a far deeper understanding of how data is being utilized in end markets.

Chips remain the fundamental building blocks, but the focus is now utilization of data for specific markets rather than processing data for all markets. Ultimately this will spur demand for huge volumes of chips. The big question is what kinds of chips, at what nodes, and how business models will need to change to accommodate these end market shifts.

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