The Power Problem

For the past few years, EDA companies have been warning chipmakers that power will become the biggest issue they face at future nodes. They were right.

While it may not be the only big problem—after all, the number of issues at each new tick of Moore’s Law is growing—power is certainly one of the most challenging and by far the most pervasive. In fact, the warnings about just how pernicious a problem it has become are beginning to resemble the famous Far Side cartoon about objects in the mirror being closer than they appear.

There are some important technology advances in this space. Fully-depleted SOI is one. Stacked die, particularly in 2.5D configurations, are another. 3D-IC are still a work in progress.

FinFETs are further along, and the advantage is that they reduce leakage at the gate. What they don’t do is reduce power density—particularly dynamic power density. The result is that thermal measurements taken at the bottom of tens of millions of tightly packed finFETs are different than measurements taken at the top. And as more metal layers are added into die, heat becomes a recurring issue for which there is no easy answer—similar to the problems researchers are wrestling with in stacked die configurations.

That’s only part of the problem, of course. Thin wires create their own source of heat. And densely packed SoCs are prone to electromigration and electromagnetic interference. Add in more power islands and there are enough unknowns to affect signal integrity, power integrity, and the functionality of an SoC.

The question now isn’t how to deal with these problems. Smart engineers can devise solutions to just about anything, given enough resources. If there isn’t more time, throw more engineers at the problem and amortize the cost over the life of a chip or derivative chips. If they can’t solve the problem with simulators, give them access to emulators. And if electrons ultimately become too difficult to work with, as IBM predicts, there are options with optical communication.

But power is unique because it affects everything. It’s not a single problem. It’s an addendum to every other problem and the cause of entirely new ones. And the only way to get a grasp on its magnitude is to understand how interactions of formerly separate areas of design can affect power. What’s needed is a giant model of everything, so that it can be verified and signed off with confidence. This is an enormous task, and it means integrating an understanding of power into well-established design flows, from architecture through to manufacturing. And even then, there is still the nagging concern that software downloaded from the Internet can ruin a lot of hard work.

What is becoming clear as we move forward is that none of this can be solved by any single company, no matter how large or advanced. It has to be solved by an ecosystem working together on solutions, standards, and sharing information. Even worse, it has to be solved yesterday. While tools vendors may see this as a golden opportunity, the opportunity will be far greater if everyone works together—not something for which EDA is always a shining example.

The upside for dealing with power effectively is huge, and the market will continue to grow as mainstream chipmakers begin encountering some of the same issues that giant chipmakers in markets such as mobile phones and computers have been wrestling with for several process nodes. Even the Internet of Things will require a deep understanding of power-related issues. And in the future, so will everything else, including those attached to an energy source with a plug.

But there’s also a potential downside in a high-profile failure—the proverbial $100 million mistake. That would reflect badly on the entire industry, including those who had no part in that failure. There’s a lot riding on cooperation when it comes to power. The entire industry has to roll up its sleeves and work together to get this right. The clock is ticking.

—Ed Sperling