Techniques to reduce the requirements for test points without sacrificing coverage.
Design for manufacturing (DFM) has become a proactive part of the design process, but the same cannot be said for DFT. Whereas “left-shifting” DFM has reduced manufacturing problems, increased yield, reduced scrap levels, and simplified engineering rework, testability-related improvements have stayed flat during that same time. Unfortunately, as assembly costs have come down, and test-related costs have remained flat, in percentage terms, test is now a significant portion of modern electronics assembly costs.
This paper describes the many techniques that can be used to reduce the requirements for test points across a design without compromising coverage. To read more, click here.
Experts at the Table, part 1: Shrinking features isn’t enough anymore. The big challenge now is how to achieve economies of scale and minimize complex integration issues.
Rising costs and gaps in equipment emerge as technology scales; new tools under development.
Explosion of data is forcing significant changes in where processing is done.
EUV is the clear winner down to 5nm, but what comes after that may be a combination of tools and techniques.
New market opportunities and global competitiveness are limited by qualified people.
Researchers digging into ways around the von Neumann bottleneck.
The promise of advanced packaging is being able to integrate heterogeneous chips, but a lot of work is needed to make that happen.
Better algorithms and more data could bolster adoption, particularly at advanced nodes.
30 facilities planned, including 10/7nm processes, but trade war and economic factors could slow progress.
New architectures, packaging approaches gain ground as costs increase, but shrinking features continues to play a role.
Improvement still needed for uptime, defectivity, line edge roughness and process flows.
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