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Scaling Sideways

Why the next steps in device scaling will break the old rules.

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The next steps in semiconductor technology don’t follow the same vectors. While 3nm chips are likely to roll out at some point in the future, it’s not clear what the business case will be for developing them.

What’s clear is the number of companies developing chips at that node will shrink to a handful (or less), because they’re going to be far too expensive to design, verify and manufacture. A single respin could bankrupt a smaller company, which makes it increasingly unlikely that anyone will try to put everything into a 3nm SoC. Integration, power management, and even electron tunneling through increasingly thin dielectrics will require a much tighter set of design rules, including more regular shapes to maintain signal integrity and yield. But for that much of an investment, chipmakers will demand more design freedom rather than less, pointing the needle in a different direction for how chips are designed and manufactured

Chips made at the most advanced nodes will still be manufactured in the highest volume, because that’s the only way to justify the development cost. But there will be fewer new designs, and possibly fewer iterations of those designs because even derivative chips are becoming more complicated and expensive.

This isn’t necessarily bad news for the semiconductor industry. For one thing, it coincides with the growth of a number new markets that have never existed before. In fact, the flattening of the growth curve in mobile phones could not have occurred at a more propitious time. An explosion in chips designed for automotive, cryptocurrency mining, cloud, AI, machine learning, deep learning, IIoT and increasingly the IoT collectively have turned that market flattening into a non-issue. Collectively, the number of chips required for all of these markets will dwarf the number of chips made for the mobile phone market, and most of them are not just generic sensors.

Looked at from another angle, computing is becoming more mobile and less defined by a single device. This is the only way to deal with an explosion of data, which needs to be processed or at least pre-processed across a mesh of devices, rather than centrally. That helps explain why the pendulum has begun to swing back from designing everything in software to designing much more in hardware. Hardware is faster, requires less power, and it’s more secure.

But it doesn’t necessarily have to be hardware as we’ve come to know it, either. A flexible hybrid device can be printed on a piece of plastic or conductive fabric. And while we are used to buying electronics with the expectation that they will work for at least several years, some of these devices may be disposable or have much more limited lifespans.


Fig. 1: FHE examples. Source: SEMI

There are enough improvements in traditional packaging, as well, to change the chip landscape. Foundries and chip design houses report a growing number of 3D-ICs under development with memory stacked on logic and connected using through-silicon vias. It will take some time to figure out how 3D-ICs compare with 2.5D or high-end fan-outs in terms of power, performance and cost, but the fact that these are under development is a sign of how much progress has been made over the past couple of years.

How much of this makes it into edge devices versus cloud-based devices is a question being asked across the supply chain these days. The idea that everything can be processed in the cloud doesn’t make sense from a data transfer standpoint because there is far too much data to transfer economically or efficiently. On top of that, it adds security risks that are unnecessary.

Add to this list quantum computing, silicon photonics, neuromorphic and other non-von Neumann architectures, and the worry about how many transistors can be packed into a given area seems far less relevant. The bigger question is how far the industry can scale in other directions, and what kind of compute architectures will need to be integrated to make all of this work. Faced with the exorbitant costs and diminishing returns of device scaling, the entire semiconductor industry has hit the reset button, and that has opened up all sorts of options that never existed in the past.



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