Shifting Left: Early Multi Physics Analysis For STCO

With the economics of transistor scaling no longer universally applicable, the industry is turning to innovative packaging technologies to support system scaling demands and achieve lower system cost. This has led to the emergence of a system technology co-optimization (STCO) approach, in which an SoC is disaggregated into smaller modules (also known as chiplets) that can be asynchronously designed by dispersed teams and then combined into a larger, highly flexible system using chiplet-based package design, which may involve 3D packaging.

STCO brings many benefits but also new challenges. It enables teams to work in a concurrent yet asynchronous manner using dispersed design teams. Each design fraction can be worked on concurrently by different teams independently of each other. This allows us to choose the optimal processes for each fragment of the design.

However, to do this, the data for all the fragments must come together at some point, and this point is in the package planning. This is when we reassemble the disaggregated SoC functional blocks (chiplets) and examine the packaging options.

The partitioning, or disaggregation, that was made will impact our ability to build a working package as well as package costs. It’s clearly important how that disaggregation is made, yet it’s made by teams that generally don’t have the downstream insight or means to consider the packaging impact of their decisions.

This is the main challenge we are looking to solve: How to reintegrate the design fractions into an early package prototype that has enough information to drive multi-physics analysis to help guide the partitioning. This includes evaluating the connectivity between design fractions. This analysis gives us critical information. By feeding that gained knowledge back to the silicon team, they possess invaluable information to help reconsider the partitioning (if needed).

This is what we mean by a shift-left approach, where analysis is performed very early and the results are used to drive design decisions as well as make corrections to mitigate the risk of verification failures later in the design flow. This article examines how such early analysis in complex high density advanced packaging (HDAP) flows enables designers to spot potential issues early to avoid built-in constructs that cause design failures and require major redesign work.

Informing partitioning with early analysis

It would be easy if partitioning was function block based. Designers may look at a block diagram of the design and make each block a design fraction. Unfortunately, it’s not quite that simple with STCO.

We need to consider things like the performance of each fraction and how it communicates with other fractions at a more detailed level. For example, will 3D stacking a block result in a performance and power gain or cause a thermal issue?

We are looking to get a higher performing, lower power solution. Regardless of how we partition, there are always multiple partitioning and integration options: finding the right one is what STCO is all about. There are likely more than one good solution, so to find out which of these is best, we build a package prototype that we can use to analyze and weigh each partitioning option of interest.

We build the package prototype incrementally and refine it as data becomes more refined over time (figure 1).

Fig. 1: Early package prototype.

At the package prototype level, we are first able to estimate power integrity and signal integrity, so the initial best effort partitioning needs to become a package prototype.

The package prototype is just what the name implies, a model of the intended package, not a detailed implementation. We know the size of the design’s functional blocks or chiplets. We know their signals, and through a SystemVerilog description of the system, we know how they connect to each other. Using a Verilog visualization tool, we get a clear overview of the circuitry, as it displays a graphic representation of the Verilog code (figure 2).

Fig. 2: Visualizing SystemVerilog in graphic form.

We may—or may not—have physical die information through LEF/DEF at this stage, but if we have, we can use it for a more detailed prototype.

We can now start by calculating the number of power and ground bumps we need for each module and build a preliminary bump map. This data is enough to take our package prototype into power integrity tools and do some very early, preliminary analysis that will tell us if it looks OK or if we have any trouble areas (figure 3).

Fig. 3: Power integrity simulation at the prototype level.

We would also characterize the signal I/Os and run preliminary signal integrity analysis to see if various 3D stacking configurations can give us the results we are looking for and, more importantly, if it fails at this level.

Essentially, we are packing more silicon into smaller area by extending along the Z axis: Volume. It’s obvious that the more we integrate into a small volume, the greater the chances that we will create a thermal problem. For that reason, early thermal estimation is as vital as signal integrity and power integrity. Since we are still early in the design phase, we cannot do a detailed simulation of any domain, but again, we can get quite far with what we do know. This is because the package prototype gives us the physical representation and the silicon design gives us an estimate on power, and we feed these into a 3D thermal simulator. 3D because these packages are truly 3D structures, and even though it is an early estimation, to simplify the package as a 2D structure is too trivial to be of value (figure 4).

Fig. 4: Thermal prototyping.

We have covered signal integrity, power integrity, and thermal, but since we have a complete 3D assembly model—aka a digital twin—we can, when there is a need, expand early analysis into mechanical stress, warping, die attach failures, metal cracking, and other physical effects. The key is that we use early IP partitioning to create a package prototype, perform meaningful simulations very early, and use the results to adjust partitioning.

Early analysis is not a replacement for more accurate simulations or package and assembly level verification—and as systems get more complex in every aspect, a final, 3D, full assembly verification is the only way to ensure success. As part of the early planning and creation of the 3D package assembly model, we also define the logical connectivity model that can be used to drive early verification, which can happen before physical design (place-and- route) of the package assembly. This enables executing multiple verification runs en route to completion — which will help identify issues early that could derail or delay a project if found at tape out. Early is the shift left keyword.

How do we know that the package prototype is correct? We take Verilog from the package prototype and use simulation to compare that against the original Verilog.

Conclusion

Early system partitioning and integration planning can have a profound impact on physical implementation in areas like power integrity, signal integrity, thermal performance, package warping, and mechanical stress. If partitioning and integration are not properly managed, they can make the entire product fail. In the partitioning process, it’s not possible to see the physical consequences of a partitioning option. As this is early in the design phase, not enough details are known to make accurate detailed simulations, but there is enough to make fast, approximate analysis to help catch issues.

We suggest a process where ASIC partitioning is fed forward to package prototyping early on, so the physical effects can be analyzed. Solutions derived in package prototyping, guided by multi-physics analysis, is handed back to the silicon teams to help drive IP partitioning and enable the IC design teams to make better, more educated decisions at a stage where partitioning can be changed before the design is too far along and costs of fixing problems become prohibitive. In other words, you can make decisions earlier.

Following this shift-left philosophy will help your teams realize tomorrow’s innovations today.

For more on STCO and this shift-left approach, see the Siemens EDA whitepapers Using a System Technology Co-Optimization (STCO) Approach for 2.5/3D Heterogeneous Semiconductor Integration and Heterogeneous Chiplet Design and Integration: Bringing a New Twist to SiP Design.