A new technical paper titled “SRAM and Mixed-Signal Logic With Noise Immunity in 3nm Nano-Sheet Technology” was published by researchers at IBM T. J. Watson Research Center and IBM.
Abstract
“A modular 4.26Mb SRAM based on a 82Kb/block structure with mixed signal logic is fabricated, characterized, and demonstrated with full functionality in a 3nm nanosheet (NS) technology. Designed macros utilize new circuits for supply boosting, read, and write assist techniques. The proposed circuits are evaluated extensively and compared to prior techniques. Statistical simulations are used to predict the benefits of these circuits in the context of dual supply use. Through programmable local clock and wordline (WL) pulsewidths, SRAM cell margins and speeds are demonstrated through hardware measurement. Stability assists as well as dual supply techniques are used to demonstrate how noise can be suppressed during traditional memory operations (single WL on), as well as to support mixed-signal logic block operation (multiple WLs on). Functionality is shown down to a cell supply of 0.45V with an estimated margin/speed of 6 GHz for SRAM cells (High Density-0.026μm2, and High Current -0.032μ m2).”
Find the technical paper here. January 2025.
R. Joshi et al., “SRAM and Mixed-Signal Logic With Noise Immunity in 3nm Nano-Sheet Technology,” in IEEE Open Journal of the Solid-State Circuits Society, doi: 10.1109/OJSSCS.2024.3524495.
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