Chip Industry Technical Paper Roundup: May 26


New technical papers recently added to Semiconductor Engineering’s library: Technical Paper Research Organizations SHIP: SRAM-Based Huge Inference Pipelines for Fast LLM Serving 🔗 Nvidia, Groq Not All Thoughts Need HBM: Semantics-Aware Memory Hierarchy for LLM Reasoning 🔗 USC, University of Wisconsin-Madison Water-based, large-scale transfer of... » read more

Scalable Photomask Optimization With Morphological Learning (SUNY Buffalo, VU, IBM)


A new technical paper, "MorphOPC: Advancing Mask Optimization with Multi-scale Hierarchical Morphological Learning," was published by researchers at University at Buffalo, Villanova University, and IBM T. J. Watson Research Center. Abstract "As feature sizes shrink to the nanometer scale, accurately transferring circuit patterns from photomasks to silicon wafers becomes increasingly chall... » read more

Research Bits: Jan. 12


Wafer-scale two-photon lithography Researchers from Lawrence Livermore National Laboratory (LLNL) and Stanford University demonstrated a two-photon lithography (TPL) platform for wafer-scale manufacturing. The TPL platform uses large arrays of metalenses to split a femtosecond laser into more than 120,000 coordinated focal spots that write simultaneously across centimeter-scale areas. The a... » read more

Chip Industry Technical Paper Roundup: Jan 6


New technical papers recently added to Semiconductor Engineering’s library: [table id=510 /] Find more semiconductor research papers here. » read more

Reliability Extension Architecture For Cost-Effective HBM (RPI, ScaleFlux, IBM TJ Watson)


A new technical paper titled "Making Strong Error-Correcting Codes Work Effectively for HBM in AI Inference" was published by researchers at Rensselaer Polytechnic Institute, ScaleFlux and IBM T.J. Watson Research Center. Abstract "LLM inference is increasingly memory bound, and HBM cost per GB dominates system cost. Current HBM stacks include short on-die ECC that tightens binning, raise... » read more

Chip Industry Technical Paper Roundup: Dec. 16


New technical papers recently added to Semiconductor Engineering’s library: [table id=501 /] Find more semiconductor research papers here and in the most recent Chip Industry Week in Review. » read more

Comparing Quantum Chemistry on Quantum Hardware (Rensselaer, IBM)


A new technical paper titled "From Promise to Practice: Benchmarking Quantum Chemistry on Quantum Hardware" was published by researchers at Rensselaer Polytechnic Institute and IBM T.J. Watson Research Center. Abstract  "We provide a systematic evaluation of the sample-based quantum diagonalization (SQD) method for electronic structure based on the W4-11 thermochemistry dataset, comprisi... » read more

Open-Source And Royalty-Free Confidential Computing For Embedded RISC-V Systems (IBM, Max Planck)


A new technical paper titled "ACE: Confidential Computing for Embedded RISC-V Systems" was published by researchers at IBM Research, IBM T.J. Watson Research Center, Max Planck Institute for Software Systems (MPI-SWS). Abstract "Confidential computing plays an important role in isolating sensitive applications from the vast amount of untrusted code commonly found in the modern cloud. We a... » read more

Thermally Aware Chiplet Placement Algorithm Based on Automatic Differentiation (MIT, IBM)


A new technical paper titled "DiffChip: Thermally Aware Chip Placement with Automatic Differentiation" was published by researchers at MIT and IBM. Abstract "Chiplets are modular integrated circuits that can be combined to form a larger system, offering flexibility and performance enhancements. However, their dense packing often leads to significant thermal management challenges, requiring ... » read more

SRAM With Mixed Signal Logic With Noise Immunity in 3nm Nanosheet (IBM)


A new technical paper titled "SRAM and Mixed-Signal Logic With Noise Immunity in 3nm Nano-Sheet Technology" was published by researchers at IBM T. J. Watson Research Center and IBM. Abstract "A modular 4.26Mb SRAM based on a 82Kb/block structure with mixed signal logic is fabricated, characterized, and demonstrated with full functionality in a 3nm nanosheet (NS) technology. Designed macros ... » read more

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