Technical Paper Roundup: Sept 5

Quantum memory; EUV mask absorbers; 10T SRAM for AI edge processors; HW design and verification; distributed batteries for 3D ICs; formally modeling a security monitor for VM confidential computing; accelerating autonomous vehicle validation and verification; graphene nanoribbons in a multigate transistor geometry.


New technical papers added to Semiconductor Engineering’s library this week.

Technical Paper Research Organizations
High-threshold and low-overhead fault-tolerant quantum memory IBM T.J. Watson Research Center and MIT-IBM Watson AI Lab
Ru/Ta bilayer approach to EUV mask absorbers: Experimental patterning and simulated imaging perspective KU Leuven and imec
An energy-efficient 10T SRAM in-memory computing macro for artificial intelligence edge processor Atal Bihari Vajpayee-Indian Institute of Information Technology and Management
PEak: A Single Source of Truth for Hardware Design and Verification Stanford University
On-Chip Batteries as Distributed Energy Sources in Heterogeneous 2.5D/3D Integrated Circuits University of Florida and Brookhaven National Laboratory
Towards a Formally Verified Security Monitor for VM-based Confidential Computing IBM Research and IBM T.J. Watson Research Center
PolyVerif: An Open-Source Environment for Autonomous Vehicle Validation and Verification Research Acceleration Florida Polytechnic University, Embry-Riddle Aeronautical University, Tallinn University of Technology, and Acclivis Technologies
Contacting individual graphene nanoribbons using carbon nanotube electrodes Swiss Federal Laboratories for Materials Science and Technology, Peking University, University of Warwick, National Center for Nanoscience and Technology (China), Max Planck Institute for Polymer Research, University of Bern, University of Basel, and ETH Zurich

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