Stacking Memory On Logic, Take Two

3D-ICs are gaining a foothold, but it’s still not easy.


True 3D-ICs, where a memory die is stacked on top of a logic die using through-silicon vias, appear to be gaining momentum.

There are a couple reasons why this is happening, and a handful of issues that need to be considered before even seriously considering this option. None of this is easy. On a scale of 1 to 10, this ranks somewhere around 9.99, in part because the EDA tools needed to remove some of the guesswork are still being developed.

The reason anyone would even consider this in the first place is this kind of performance improvement isn’t available any other way, particularly for traditional chip architectures. The move from 7nm to 5nm will generate performance improvements somewhere in the 20% range, depending upon whose process is being used. (Given the divergent processes, it’s difficult to find independent verification of the numbers provided by Samsung and TSMC, and chipmakers working at those nodes typically don’t like to discuss their numbers for competitive reasons.)

By stacking memory on logic, performance increased by abouty 37% boost, along with a 39% improvement in power, according to Sung Kyu Lim, professor in Georgia Tech’s school of electrical and computer engineering. In a presentation at the Arm Research summit this week, Lim said stacking die provides the equivalent of one extra node of power and performance improvements even using metrics from previous nodes

That’s impressive, particularly when combined with the benefits of traditional scaling at the most advanced nodes, and it’s something the foundries, the equipment makers, and the OSATs have been preparing for on and off over the past several years.

The initial thinking was that logic would be stacked on logic to boost density, with another layer of memory possibly sandwiched between them. In theory, that would significantly shorten the distance between the die and speed up signals in critical datapaths. The problem is the density of both the logic and the memory generate heat, and there is no way to remove that heat without some exotic methods such as microfluidics, which have never been proven in volume production.

Memory on logic improves the thermal picture because two sides are exposed, but not enough. So while floor-planning is already challenging at advanced nodes, layouts now need to consider where to put various components on a chip for thermal, noise and performance reasons, and they need to lined up perfectly so the tiny holes drilled for vias through one die line up with the other die. This already is being done with 3D memory, but it’s a big change for putting memory on logic where there is an assortment of heterogeneous devices.

Moreover, there are still gaps in the EDA tools. Some of these are still made for planar designs, and while they can be tweaked for 3D-ICs, it’s not a perfect fit. Some adjustments will be needed.

All of this needs to be mapped out up front, according to Lim. That includes a 3D library exchange format (LEF) and power delivery network, among other things, and it requires floor-planning to isolate the heat generated by the die so they don’t overlap and cook the chips. Clocks and timing also need to be considered in three dimensions rather than two.

Nevertheless, the fact that full 3D-ICs are being developed represents something of a breakthrough for high-performance chips, such as those designed for data centers and for extremely limited form factors, such as those that will be required in edge inferencing devices. The bottom line: Never underestimate what can be done by very determined teams of semiconductor researchers, scientists and engineers.


SB says:

Have people tried nano-scale Thermo-Electric Cooling applied between Logic-Memory or Logic-Logic.

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