Strategies For Meeting Stringent Standards For Automotive ICs

It may surprise you, but when it comes to chips in electronic braking systems, airbag control units, and more, automotive manufacturers are still using 10-year-old technology — and with good reason.

For the automotive industry, the reliability, stability, and robustness of electronic components are critical, especially when it comes to meeting the stringent Automotive Electronics Council (AEC) Q100 standards that fabs need to follow. Some in the industry would not only rather keep using proven older chips over new ones, but they might even call for the construction of new fabs for older chips. In other words, tried and true is better than new and improved.

While helping a manufacturer that builds various sensor chips for the automotive industry, I witnessed how challenging and time consuming it was for a fab to make even minor changes to production lines. We had to set up a separate data flow without impacting the current production line and prove for six months that the change we made hadn’t adversely impacted production results.

To achieve the high AEC Q100 standards and others, it is critical for fabs to utilize the data and knowledge that is available to them about everything that happens to the wafer, chip, package, fab tools, process, and fab environment.

Fig. 1: Overview of how fabs achieve higher quality and reliability standards.

To accomplish this, a rigorous and thorough inspection, with the help of analytics software, is key.

Inspection recipes should be designed to not only meet production demand but also capture images for most of the appropriate defects using an intelligent sampling strategy. This strategy should take engineering rules into account and be able to incorporate stringent automotive quality standards for review.

Fig. 2: Auto die classifier at work to convert defect map into a die map during AOI image capture: The figure shows how inspection and software helped fabs reduce review by 52% and also incorporate automotive standards for binning chips during inspection time.

Based on the defect attributes and features, software leveraging machine-learning and rules-based engines can pre-classify defects and bin defective dies during the inspection process that might have been skipped otherwise to keep up with production.

For some manufacturers, these rules are needed at the lot level, not just at the wafer level. Consider this: When a defect pattern or cluster is detected on only a few wafers in a lot, how do we make sure chips that fall in the same area on the rest of the wafers in that lot are proactively binned as potential failures? For this, techniques such as lot-level guard banding/binning strategies need to be implemented so that chips that are not flagged as failures, due to the inspection recipe and/or wafer material/process challenges, can be proactively binned as reliability failures.

Time and time again, we have seen that not all defective dies fail at the electrical step, especially those with spatial signatures like scratches; this is the good-die-in-a-bad-neighborhood rule. It is engineering wisdom that a good die in a bad neighborhood is most likely to fail in later steps. In other words, even if it didn’t fail in a fab, it might fail after shipping to the customer. In industries like automotive, this is particularly critical to prevent.

To avoid this, fabs need the ability in the back end to utilize spatial signatures found on wafers in the front end as a way to avoid defective dies escaping at the wafer probe step. To deal with special defects like micro cracks, some in the industry have adopted software with machine-learning-based pattern engines and auto die-binning rules, such as neighboring die kill (NDK), to fail potentially faulty good dies in bad neighborhoods.

Like the NDK rule, reticle field-based binning is a technique that has also been adopted for the automotive industry. With reticle-based binning, if 50% or more of the dies in a reticle are bad, then the rest of the dies are proactively determined to be bad as well, just to give one example.

The advent of AI and Big Data solutions now allow fabs to implement a compute-intensive yield prediction score for devices based on complex calculation conditions (using nested defect attribute-based event and wafer probes) in kill-ratio and yield prediction models. A die-quality score can be derived from distribution-free yield prediction models across all automated optical inspection (AOI) layer steps. This allows for the passage of only highly reliable devices to the next step in the manufacturing process, thereby helping maintain device quality.

Part Average Testing (PAT) is another important outlier detection technique that fabs building devices for the automotive industry follow. PAT helps remove potential abnormal parts early in the manufacturing process. This contributes to decreased manufacturing costs by reducing device failures in the back end and field. In addition, there is the cost of return materials authorization (RMA)/failure analysis and the opportunity lost by fabs for shipping dormant, potentially defective, dies to their customers. If fabs ship parts that later fail in the field, that is a reliability issue that can cost them serious business.

It is common for fabs to follow both static and dynamic PAT. Machine-learning-based yield and process optimizer engines that are used to continuously determine the relationships between different tests can also be applied to find device outliers that are otherwise difficult to find.

In our experience, fabs face challenges reducing overkill and underkill at the final test. While dynamic PAT helps to catch more chips with reliability issues, there is a compromise between overkill and yield. To overcome this challenge, fabs need to combine software-based genealogy technology with dynamic PAT to better capture reliability issues with less overkill.