Supply Chain Catch-Up

It will take years before most chip makers are ready to deal with the latest innovations.


There always will be a few big companies marching to the latest process node available to them. The problem these days isn’t their commitment to pushing forward. It’s the baggage train following them. It’s getting longer, more diverse, and in some cases, it’s falling out of sync.

The foundries are out in front with 14nm finFETs, and they’re already working on 10nm transistors—possibly with a 14nm process on the back end. They have taped out test chips, have working prototypes, and they’ve got many of the kinks worked out.

The problem is that while some of the EDA tool chain has been working side by side, the entire tool chain has not. And even though the big EDA companies have been pitching end-to-end solutions, chipmakers don’t want to get locked into any single vendor’s flow.

Consider the recent ruckus over dueling power formats for verifying chips. Two standards would have been a non-issue if chipmakers had opted for one vendor’s tools. Instead, they pick a combination of point tools and best-in-class pieces out of multiple vendors’ flows, then cobble them together into their own customized version. The result was a half-dozen years of complaints, delays and hair-pulling, which only now is beginning to subside.

That’s only one piece of the puzzle, too. Lithography is in flux, which means we may soon witness the advent of triple or quadruple patterning. The departure of ASML CEO Eric Meurice and the ascension of CFO Peter Wennink to the top post doesn’t bode well for getting EUV out the door anytime soon. Whether there is a suitable replacement for EUV remains a matter of speculation. If the industry opts for directed self-assembly as a replacement strategy, the entire EDA industry will have to revamp its tools.

And the supply chain still isn’t prepared for 3D-ICs, even though many of the technologies necessary to make this possible appear to be ready. The issues of liability from two known good die producing a bad chip remain unsolved, so at least for the next couple of years this technology will see only limited use. Stacked die using an interposer layer will likely progress faster, but how much faster remains to be seen.

Nor is this issue strictly confined to fabless companies. IDMs and fabless companies are both facing the same hurdles. We are at a point where the big equipment makers and developers of the processes have made great advancements, but the rest of the supply chain necessary to churn out semiconductors will take years to fully catch up. This is difficult stuff, to be sure, and not everything moves at the same pace. But in this case, we may be reaching the point where everything will begin to move more slowly, and the various pieces are so complex and so expensive that no one—not even Intel, IBM or Samsung—can afford to progress any faster than the supply chain allows.

What an odd way to level the playing field.

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