System-Level Test: Where Does It Fit?

Why an evolution in the test flow is so critical to the cost of test.


Our second C-Brief discusses where system-level test (SLT) best fits into your semiconductor test workflow. With automated testing equipment (ATE), a traditional workflow may consist of:

  • Wafer sort (WS)
  • Burn-in after packaging (BI)
  • Combination of structural testing (ST) and functional testing (FT).

As demands on high-volume manufacturing shift in response to wider industry and commercial trends, a greater number of manufacturers are adopting SLT to augment and even partially replace this traditional process. This evolution in the test workflow is putting chipmakers in stronger positions to meet the demands of the future and challenging the assumption that an additional insertion increases cost of test (CoT).

This C-Brief white paper discusses SLT’s versatile capabilities to create opportunities for workflow consolidation and how exactly it fits into tomorrow’s semiconductor ecosystem. To read more, click here.

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