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System-Level Test: Where Does It Fit?


Our second C-Brief discusses where system-level test (SLT) best fits into your semiconductor test workflow. With automated testing equipment (ATE), a traditional workflow may consist of: Wafer sort (WS) Burn-in after packaging (BI) Combination of structural testing (ST) and functional testing (FT). As demands on high-volume manufacturing shift in response to wider industry and com... » read more

Looking At Test Differently


Wilhelm Radermacher, executive advisor at [getentity id="22816" e_name="Advantest"], sat down with Semiconductor Engineering to discuss how the impact of rapid market changes, advanced packaging approaches and increasing complexity on test strategies and equipment. What follows are excerpts of that conversation. SE: As we move into new markets where use models and stresses on devices are dif... » read more

How Much Testing Is Enough?


As chipmakers move towards finer geometries, IC designs are obviously becoming more complex and expensive. Given the enormous risks involved, chipmakers must ensure the quality of the parts before they go out the door. And as part of quality assurance process, that requires a sound test strategy. But for years, IC makers have faced the same dilemma. On one hand, they want a stringent test me... » read more