IP Integration Challenges Increase


Semiconductor Engineering sat down with Chris Rowen, CTO of [getentity id="22032" e_name="Cadence"]'s IP group; Rob Aitken, an [getentity id="22186" comment="ARM"] fellow; Patrick Soheili, vice president of product management and corporate development at [getentity id="22242" e_name="eSilicon"]; Navraj Nandra, senior director of marketing for DesignWare analog and mixed-signal IP at [getentity ... » read more

GF Closes On IBM Chip Business Purchase


By Ann Steffora Mutschler, Ed Sperling and Mark LaPedus GlobalFoundries completed its acquisition of IBM's Microelectronics Group today, creating a behemoth that is expected to extend well beyond the combined footprint of the existing companies. To begin with, GlobalFoundries will get two additional fabs, one of which makes RF SOI chips. But while IBM was hesitant to expand that business ... » read more

Executive Insight: Wally Rhines


Wally Rhines, chairman and CEO of Mentor Graphics, sat down with Semiconductor Engineering to talk about what's changing across a wide swath of the industry, where the new opportunities will be, when security will become a real opportunity for EDA, and why Moore's Law will die but progress will continue forever. SE: Looking back over the past year, what's changed and where are the possible r... » read more

Foundries Expand Planar Efforts


Competition is heating up in the leading-edge foundry business, as vendors begin to ramp up their new 16nm/14nm finFET processes. But that’s not the only action in the foundry arena. They are also expanding their efforts in the leading-edge planar market by rolling out new 28nm and 22nm processes. On one front, TSMC is offering new 28nm variants, based on bulk CMOS technology. And on an... » read more

Getting Over Overlay


Chipmakers continue to migrate to the next node, but there are signs that traditional IC scaling is slowing down. So what’s causing the slowdown? Or for that matter, what could ultimately undo [getkc id="74" comment="Moore's Law"]? It could be a combination of factors. To be sure, IC design costs and complexity are soaring at each node. Scaling challenges are also playing a role. And ov... » read more

Speeding Up E-beam Inspection


Wafer inspection, the science of finding killer defects in chips, is reaching a critical juncture. Optical inspection, the workhorse technology in the fab, is being stretched to the limit at advanced nodes. And e-beam inspection can find tiny defects, but it remains slow in terms of throughput. So to fill the gap, the industry has been working on a new class of multiple beam e-beam inspectio... » read more

SoC Integration Headaches Grow


As the number of IP blocks grows, so do the headaches of integrating the various pieces and making sure they perform as planned within a prescribed power envelope. This is easier said than done, particularly at the most advanced process nodes. There are more blocks, more power domains, more states and use-model dependencies, and there is much more contention for memories. There are physical ... » read more

The Week In Review: Manufacturing


In what was called a defensive measure by some, Intel has announced a definitive agreement to acquire Altera for $54 per share in an all-cash transaction valued at approximately $16.7 billion. Here’s what one analyst said about the deal. “We continue to believe Intel’s pursuit of Altera–at a significant premium–was based on a defensive position, rather than the purely accretive str... » read more

Big Data Needs Bigger Memory


By Rodrigo Liang Over the last few decades, the semiconductor industry has focused its considerable technical investments in accelerating software applications. Performance metrics for new semiconductor products are often correlated with their ability to lower the latency to access data required to run specific software applications. The need for increased performance from semiconductors ... » read more

What’s Different At 16/14nm?


Will finFETs live up to their promise? It depends on whom you ask, when you ask that question, and the intended application of a design. But across the semiconductor industry, there is general agreement that it's getting easier to work at the most advanced nodes as tools and flows are better understood and overall experience increases. There is no question that [getkc id="185" kc_name="finFE... » read more

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