Shootout At 28nm

By Ed Sperling - 15 May, 2014 - Comments: 0

By Ed Sperling & Mark LaPedus Samsung, Soitec and STMicroelectronics are joining forces on 28nm FD-SOI, creating a showdown with TSMC and others over the best single-patterned processes and materials and raising questions about how quickly companies need to move to the finFET technology generation. The multi-source manufacturing collaboration agreement for fully depleted silicon-on-insulato... » read more

The Bumpy Road To FinFETs

By Mark LaPedus - 15 May, 2014 - Comments: 2

The shift from planar transistors to finFETs is a major inflection point in the IC industry. FinFETs are expected to enable higher performance chips at lower voltages. And the next-generation transistor technology also could allow the industry to extend CMOS to the 10nm node and perhaps beyond. But as it turns out, finFET technology is also harder to master than previously thought. For exam... » read more

A Node By Any Other Name

By Barry Pangrle - 12 May, 2014 - Comments: 3

Have you ever wondered what gives a particular CMOS technology node its name? When we talk about 20nm, 16nm or 14nm, what exactly does that number in front of the “nm” mean anyway? Is it the first layer metal half-pitch or the gate length (and while we’re at it, is that the printed gate length, the physical gate length, or the effective gate length)? The half-pitch refers to half the m... » read more

What’s Wrong With Power Signoff

By Ed Sperling - 12 May, 2014 - Comments: 0

Power signoff used to be a checklist item before a design went to tapeout. But as power has become a critical factor in designs, particularly at advanced nodes, signing off on power now needs to be done at multiple points throughout the design flow. That alone adds even greater complexity to already complex design processes because it requires fixed reference points and scenarios for taking mea... » read more

Stopping Mask Hotspots Before They Escape The Mask Shop

By eBeam Initiative - 28 Apr, 2014 - Comments: 3

By Aki Fujimura The same types of physics-based issues that have haunted lithography for decades have started to impact mask writing as well. The increasingly small and complex mask shapes specified by optical proximity correction (OPC) that are now required for faithful wafer lithography at 28nm-and-below nodes have given rise to an increase in mask hotspots. Mask hotspots occur when the shap... » read more

The Week In Review: Design

By Ed Sperling - 18 Apr, 2014 - Comments: 0

Certifications TSMC certified Mentor Graphics’ DFM, place and route and custom IC tools, as well as its SPICE simulator, for the 16nm finFET process. The foundry also certified Cadence’s digital and custom/analog tools for that process, including physical verification, QRC extraction, timing sign off and its power integrity solution. And it certified Synopsys’ digital and custom soluti... » read more

Mask Hotspots Are Escaping The Mask Shop

By Various Writers - 16 Apr, 2014 - Comments: 0

Although the overwhelming majority of wafer production issues at the 28nm-and- below process nodes are lithography- and OPC-related, the semiconductor industry is starting to see problems caused by mask hotspots: wafer-level production issues that are caused when the shapes specified by optical proximity correction (OPC) are not faithfully reproduced on the mask. Mask hotspots will account for ... » read more

Power Moves Up To First Place

By Ed Sperling - 10 Apr, 2014 - Comments: 2

Virtually every presentation delivered about semiconductor design or manufacturing these days—and every end product specification that uses advanced technology—incorporates some reference to power and/or energy. It has emerged as the most persistent, most problematic, and certainly the most talked about issue from conception to marketplace adoption. And the conversation only grows louder... » read more

Tech Talk: Multipatterning, Take Two

By Brian Bailey - 31 Mar, 2014 - Comments: 0

Mentor Graphics' David Abercrombie continues with his whiteboard talk about coloring with advanced lithography, including what goes wrong and how to fix it. [youtube vid=HCBtvHCcbf4] » read more

How Much Will That Chip Cost?

By Ed Sperling - 27 Mar, 2014 - Comments: 1

From the most advanced process nodes to the trailing edge of design there is talk about the skyrocketing cost of developing increasingly complex SoCs. At 16/14nm it’s a combination of multi-patterning, multiple power domains and factoring in physical and proximity effects. At older nodes, it’s the shift to more sophisticated versions of the processes and new tools to work within those proce... » read more

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