Stopping Mask Hotspots Before They Escape The Mask Shop

The chip industry is facing challenges of a magnitude not seen since the early days of OPC.


By Aki Fujimura
The same types of physics-based issues that have haunted lithography for decades have started to impact mask writing as well. The increasingly small and complex mask shapes specified by optical proximity correction (OPC) that are now required for faithful wafer lithography at 28nm-and-below nodes have given rise to an increase in mask hotspots. Mask hotspots occur when the shapes produced on the mask deviate enough on a per-instance basis from the shapes designed by OPC to impact negatively on wafer quality and yield.

The biggest problem is that because current mask verification methodologies do not flag these hotspots, they are usually identified only after expensive mask production, or even after wafer production. Mask hotspots are escaping the mask shop, and catching these errors downstream is very costly in terms of both production cost and time.

In the past, the main challenge was to have sophisticated-enough OPC to ensure that the mask would produce the desired shape on the wafer. But the impacts of those physics-based issues on mask making mean that “what you get” on the mask is no longer always what you specified. The nominal contour might not be where the contour was drawn, depending on shape and context of the shape. Or, the dose margin could be worse depending on the shape and the context of the shape, making the variation from the nominal contour too large. As a result, resilience to manufacturing variation is poor for those shapes, leading to poor line-edge roughness (LER) and poor critical dimension uniformity (CDU). While some parts of variation in nominal contour can be remedied through mask process correction (MPC) – either embedded in the OPC process or in the mask shop – the problem of poor resilience to manufacturing variation must be detected and resolved in the mask shop.

Mask hotspots must be monitored shape by shape, over the entire mask. For today’s masks with complex shapes at 28nm-and-below nodes, a simulation-based approach that can verify the entire mask with each shape in its surrounding context is required.

Today’s mask-making methodology relies on mask inspection to catch mask errors other than data-handling errors (which are detected through routine XOR-based verification). Current inspection machines can catch 1D feature differences down to 10nm (4X dimensions). But, particularly for 2D features, shape-dependent differences between the actual mask shapes and the intended mask shapes of less than 10nm are not flagged by current mask inspection methodologies. SEM, AIMS and further defect-categorization tools can accurately inspect individual suspected areas, but a full-mask inspection must first flag those suspected areas. Today’s methodologies do not have such full-mask processes built in.

As masks with very small, complex shapes are becoming the norm, mask shops need a way to insure that mask hotspots are caught before they can impact wafer production. This problem will only get worse as minimum mask-shape size moves well below 60nm, as edge-placement accuracy requirements for all shapes on the mask become increasingly stringent, as mask shapes continue to increase in complexity for immersion, and as line-end-to-line-end precision becomes critical for EUV lithography and other patterning techniques.

Full-chip mask verification is the only way to prevent mask hotspots from leaving the mask shop undetected. Fortunately, with the recent advent of general-purpose graphics-processing unit (GPGPU) acceleration, this kind of extensive, full-chip simulation can be performed with practical runtimes.

Model-based mask verification (MB-MV) is an existing technology that can be applied today to this emerging problem. MB-MV offers full-chip simulation that can find mask hotspots with 1-2nm precision. GPGPU-accelerated simulation enables full-chip mask simulation within the time it takes to write the mask. MB-MV checks the nominal contours of every shape on the mask, each in its unique context. Critically, MB-MV also includes dose margin detection, so it can check not only for nominal contour but also for resiliency to manufacturing variation.

The semiconductor industry is facing a new era of mask making challenges with an impact across the entire supply chain not seen since the early days of OPC. The arrival of multi-beam writing will accelerate the importance of these challenges. Particularly for the type of mask hotspots that come from the poor resilience to a per-instance variation, we need to collaborate to create a methodology around MB-MV to stop mask hotspots from escaping the mask shop.

—Aki Fujimura is the chairman and CEO of D2S, the managing company sponsor of the eBeam Initiative.

  • preferrous

    As usual, paranoid secrecy is how the industry shoots itself in the foot.

    All aspects of leading-node mask writing+inspection are treated as ultra-super-top-secret-this-tape-will-self-destruct matters. That’s fine when you have a staff of top-flight EE’s and materials scientists to handle the EE and MS issues. But when something like parallelization comes up you’re not going to be able to attract the hotshot software CS people you need to fix the problem, and the young CS grad students who might have a fresh perspective don’t even know what the problem is because it’s all Top Secret.

    PDKs are another place this manifests, although mainly because nobody seems to want to rock the EDA-oligopoloy boat.

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