tag: 14nm

GloFo Says 28nm FD-SOI Die Cost Much Less Than 28nm Bulk HPP
By Various Writers - 17 Jul, 2013 - Comments: 0

Posted by Adele Hars, Editor-in-Chief, Advanced Substrate News ~  ~ According to Shigeru Shimauchi, Country Manager, GlobalFoundries Japan, for the same level of performance, the die cost for 28nm FD-SOI will be substantially less than for 28nm bulk HPP (“high performance-plus”). Specifically, to get a 30%  increase in performance over 28nm bulk LPS PolySiON, HPP increases die ... » read more

Seeing Spots At 10nm
By Ed Sperling - 15 Jul, 2013 - Comments: 0

By Ed Sperling The relentless march to smaller process nodes means the defects are getting smaller, more numerous, and much harder to find. That explains why Applied Materials and KLA-Tencor both introduced new defect review and classification tools last week. The move to the 1x nm is on the top of both companies’ agendas, and with that comes defects on the walls of finFETs in addition to... » read more

Experts At The Table: Changes In The Ecosystem
By Ed Sperling - 01 Jul, 2013 - Comments: 0

By Ed Sperling Semiconductor Manufacturing & Design sat down with Michael Buehler-Garcia, director of design solutions marketing at Mentor Graphics; Seow Yin Lim, group director for marketing at Cadence; Kevin Kranen, director of strategic alliances at Synopsys, and Tom Quan, director at TSMC. What follows are excerpts of that conversation. SMD: How are chipmakers working with the rest ... » read more

Experts At The Table: Changes In The Ecosystem
By Ed Sperling - 01 Jul, 2013 - Comments: 0

By Ed Sperling Semiconductor Manufacturing & Design sat down with Michael Buehler-Garcia, director of design solutions marketing at Mentor Graphics; Seow Yin Lim, group director for marketing at Cadence; Kevin Kranen, director of strategic alliances at Synopsys, and Tom Quan, director at TSMC. What follows are excerpts of that conversation. SMD: How are chipmakers working with the rest... » read more

New Reliability Issues Emerge
By Ed Sperling - 27 Jun, 2013 - Comments: 0

By Ed Sperling Most consumers define reliability by whether a device turns on and works as planned, but the term is becoming harder to define as complexity increases and systems are interconnected. Adding more functionality in less space has made it more difficult to build complex chips, and it has made it more difficult to prevent problems in those chips. Verification coverage is a persist... » read more

Inside A 450mm Metrology Consortium
By Mark LaPedus - 20 Jun, 2013 - Comments: 0

By Mark LaPedus Semiconductor Manufacturing & Design sat down to discuss 450mm metrology challenges with Menachem Shoval, a former manufacturing executive at Intel and chairman of the Metro450 consortium. The Israeli-based consortium is developing metrology technology for the next-generation, 450mm wafer size. The group consists of Intel, Applied Materials, Jordan Valley, Nanomotion, Nov... » read more

Experts At The Table: Changes In The Ecosystem
By Ed Sperling - 20 Jun, 2013 - Comments: 0

By Ed Sperling Semiconductor Manufacturing & Design sat down with Michael Buehler-Garcia, director of design solutions marketing at Mentor Graphics; Seow Yin Lim, group director for marketing at Cadence; Kevin Kranen, director of strategic alliances at Synopsys, and Tom Quan, director at TSMC. What follows are excerpts of that conversation. SMD: What’s changing in the ecosystem and ho... » read more

Extending Copper Interconnect Beyond The 14nm Node
By Various Writers - 20 Jun, 2013 - Comments: 0

Fabricating interconnects is one of the most process-intensive and cost-sensitive parts of manufacturing. To find out more about what's changing in this area and why it's so important, click here. » read more

Marching Orders
By Ed Sperling - 20 Jun, 2013 - Comments: 0

Reports back from the front lines of Moore’s Law are rather consistent—14nm and 16nm finFETs are do-able, but they’re not easy to design, verify or manufacture. In fact, the only high-volume source of production-proven finFETs at this point is Intel, which is turning them out at 22nm. A number of issues are cropping up at the most advanced nodes, and while each is ultimately solvable, ... » read more

Drowning In Data
By Ed Sperling - 13 Jun, 2013 - Comments: 0

By Ed Sperling The old adage, “Be careful what you wish for,” has hit the SoC design market like a 100-year storm. After years of demanding more data to understand what’s going on in a design, engineering teams now have so much data that they’re drowning in it. This is most obvious at advanced process nodes, of course. But it’s also true these days at more mainstream nodes such as... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy