tag: 16nm

28nm FinFETs?
By Brian Bailey - 10 Jul, 2014 - Comments: 5

One star of the upcoming 14/16nm process node is the introduction of the finFET, a fundamentally new transistor that overcomes many of the limitations associated with planar transistors. While these devices are more complex to construct—and the physical extraction processes associated with them is more complex due to an increased number of resistances and capacitances—they are seen as a tra... » read more

Why An IBM Sale Matters
By Ed Sperling - 07 Jul, 2014 - Comments: 0

The rumored sale of IBM’s semiconductor unit to GlobalFoundries could add some interesting capabilities for the foundry, including deep process technology and expertise. It also could have some far-reaching effects for the entire semiconductor industry. The reason revolves around ongoing U.S. government initiatives to improve visibility for components throughout its supply chain. IBM has b... » read more

Semiconductor R&D Crisis Ahead?
By Ed Sperling - 26 Jun, 2014 - Comments: 0

Listen to engineering management at chipmakers these days and a consistent theme emerges: They’re all petrified about where to place their next technology bets. Do they move to 14/16nm finFETs with plans to shrink to 10nm, 7nm and maybe even 5nm? Do they invest in 2.5D and 3D stacked die? Or do they eke more from existing process nodes using new process technologies, more compact designs and ... » read more

Without Moore’s Law: EDA
By Brian Bailey - 26 Jun, 2014 - Comments: 3

Semiconductor Engineering is examining the assertion about the end of Moore’s Law in a number of different ways. The special report, “Will 7nm and 5nm really happen?” looked at the technical aspects related to continuing into finer geometries. “Moore’s Law Tail No Longer Wagging the Dog” asked the question about the economics of people being able to afford to go to the latest node. ... » read more

Shootout At 28nm
By Ed Sperling - 15 May, 2014 - Comments: 0

By Ed Sperling & Mark LaPedus Samsung, Soitec and STMicroelectronics are joining forces on 28nm FD-SOI, creating a showdown with TSMC and others over the best single-patterned processes and materials and raising questions about how quickly companies need to move to the finFET technology generation. The multi-source manufacturing collaboration agreement for fully depleted silicon-on-insulato... » read more

The Bumpy Road To FinFETs
By Mark LaPedus - 15 May, 2014 - Comments: 2

The shift from planar transistors to finFETs is a major inflection point in the IC industry. FinFETs are expected to enable higher performance chips at lower voltages. And the next-generation transistor technology also could allow the industry to extend CMOS to the 10nm node and perhaps beyond. But as it turns out, finFET technology is also harder to master than previously thought. For exam... » read more

A Node By Any Other Name
By Barry Pangrle - 12 May, 2014 - Comments: 3

Have you ever wondered what gives a particular CMOS technology node its name? When we talk about 20nm, 16nm or 14nm, what exactly does that number in front of the “nm” mean anyway? Is it the first layer metal half-pitch or the gate length (and while we’re at it, is that the printed gate length, the physical gate length, or the effective gate length)? The half-pitch refers to half the m... » read more

What’s Wrong With Power Signoff
By Ed Sperling - 12 May, 2014 - Comments: 0

Power signoff used to be a checklist item before a design went to tapeout. But as power has become a critical factor in designs, particularly at advanced nodes, signing off on power now needs to be done at multiple points throughout the design flow. That alone adds even greater complexity to already complex design processes because it requires fixed reference points and scenarios for taking mea... » read more

Stopping Mask Hotspots Before They Escape The Mask Shop
By eBeam Initiative - 28 Apr, 2014 - Comments: 3

By Aki Fujimura The same types of physics-based issues that have haunted lithography for decades have started to impact mask writing as well. The increasingly small and complex mask shapes specified by optical proximity correction (OPC) that are now required for faithful wafer lithography at 28nm-and-below nodes have given rise to an increase in mask hotspots. Mask hotspots occur when the shap... » read more

Power Moves Up To First Place
By Ed Sperling - 10 Apr, 2014 - Comments: 2

Virtually every presentation delivered about semiconductor design or manufacturing these days—and every end product specification that uses advanced technology—incorporates some reference to power and/or energy. It has emerged as the most persistent, most problematic, and certainly the most talked about issue from conception to marketplace adoption. And the conversation only grows louder... » read more

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