tag: 16nm

Can Intel Dethrone The Foundry Giants?
By Mark LaPedus - 12 Dec, 2013 - Comments: 3

The leading-edge foundry business isn’t for the faint of heart. It requires deep pockets and sound technology to keep pace in the chip-scaling race. And despite pouring billions of dollars into new fabs and processes, foundries are competing for fewer customers at each node. Given the difficult business conditions, only a handful of vendors can afford to compete in the high-end foundry bus... » read more

New Challenges Emerge With FinFETs
By Ed Sperling - 05 Dec, 2013 - Comments: 0

Working at advanced process nodes is always tricky. There are new things to worry about and more rules to deal with initially, yet the promised benefit is improved performance, power and area, or cost. But at the next process node, and the one after that, there are so many variables coming into play that trying to make sense of the PPA equation is becoming much more difficult. Early reports ... » read more

Seven Ways To Improve PPA Before Moving To FinFETs
By Ed Sperling - 05 Dec, 2013 - Comments: 0

Henry Ford wrote in his autobiography, “Any customer can have a car painted any color that he wants so long as it is black.” And for decades, the semiconductor industry has marched to a similar theme set by Moore’s Law. But with the transition to finFETs harder than it first appeared, questions are beginning to pop up that is fueling a new level of confusion. While the growing list of... » read more

The Week in Review: System-Level Design
By Ed Sperling - 15 Nov, 2013 - Comments: 0

Cadence unveiled its next-gen power signoff tool, this one based upon parallel execution across multiple processors. The result is 10x speed improvement, according to the company. The signoff solution already is certified for TSMC’s 16nm finFET process for IR drop analysis and EM rule compliance, two of the big concerns with finFETs. Synopsys teamed up with CEVA to improve PPA for CEVA’s... » read more

Paving The Way To 16/14nm
By Ed Sperling - 07 Nov, 2013 - Comments: 0

The move to the next stop on the Moore’s Law road map isn’t getting any less expensive or easier, but it is becoming more predictable. Tools and programs are being expanded to address physical effects such as electrostatic discharge (ESD), electromigration and thermal effects from increased current density. Any or all of these three checklist items can affect the reliability of a chip. A... » read more

The Week In Review: Oct. 18
By Mark LaPedus - 18 Oct, 2013 - Comments: 0

By Mark LaPedus & Ed Sperling The problems continue with extreme ultraviolet (EUV) lithography. ASML promised to deliver an 80 Watt power source by year’s end. Now, the company said it only will have a 70 Watt source by mid-2014. “We are focusing on reaching the 70 Watts by the middle of next year,” said Peter Wennink, ASML’s CEO, in a conference call to discuss the company’s res... » read more

EDA Shows Continued Growth
By Ed Sperling - 16 Oct, 2013 - Comments: 0

EDA and IP revenue jumped 3.8% in Q2 to $1.65 billion, up from $1.59 billion in the same period in 2013, spurred by the need for new tools to design, create and verify SoCs using 16/14nm finFETs. Sequentially, the numbers reported by the EDA Consortium were down slightly from Q1, but the four-quarter moving average—considered a more reliable number because tools sales are long-term investm... » read more

The Brave New World Of FinFETs
By Ed Sperling - 10 Oct, 2013 - Comments: 0

SoCs using 16nm and 14nm finFETs are expected to begin rolling out next year using a 20nm back-end-of-line process. While the initial performance and power numbers are looking very promising, the challenges of designing and building these complex chips are daunting—and there are more problems on the way. First, the good news. Initial results from foundries show a 150% improvement in perfor... » read more

Reliability Challenges In 16nm FinFET Design
By Arvind Vel - 10 Oct, 2013 - Comments: 1

As the IC industry rapidly adopts the 16nm technology node, IC designers are faced with a new wave of reliability challenges. The 16nm node has introduced several changes in the way that the devices are fabricated and how the metal stack-up is built. On one hand designers gain speed, leakage and density improvements. On the other, reliability engineers need to address the narrowing electromigra... » read more

Power Grid Analysis Heats Up At 20nm
By Ann Mutschler - 12 Sep, 2013 - Comments: 0

By Ann Steffora Mutschler Do a simple Internet search for the term ‘power grid analysis’ and most of the results are academic sources. However, given the physics of either planar or finFET at 20nm and below, the power grid will see significant impacts. Overall, there are a number of technical implications of migrating from 28nm down to 20, 16 or 14 nm, with further impacts of moving fro... » read more

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