tag: 20nm

To 7nm And Beyond
By Ed Sperling - 21 Jul, 2016 - Comments: 4

Gary Patton, chief technology officer at [getentity id="22819" comment="GlobalFoundries"], and Thomas Caulfield, senior vice president and general manager of Fab 8, sat down with Semiconductor Engineering to discuss future directions in technology, including the next rev of FD-SOI, the future of Moore’s Law, and how some very public challenges will likely unfold. SE: What do you see as the... » read more

Abundant Change Ahead
By Brian Bailey - 06 Jul, 2016 - Comments: 1

There is nobody who would question the amazing ride that semiconductors have been on for the past 50 years. It has been described as the longest running exponential that humankind has ever been a part of—and it is not over yet. Still, the future is very likely to be substantially different from the past. It is almost natural for us to see a trend and assume it will continue. There have bee... » read more

TSMC: Onward to 5nm
By Barry Pangrle - 10 Mar, 2016 - Comments: 0

TSMC’s financial results for the Q4 of 2015 were released in January and showed an 8.5% revenue drop compared to the previous year, and a 3.5% decrease compared to Q3 (all in NT$). For the full year though, TSMC said it had again achieved record sales, with revenue for the full year up over last year by 10.6% in NT$ (5.7% in US$). President and co-CEO Mark Liu reported that TSMC sees a red... » read more

More Choices, Less Certainty
By Ed Sperling - 04 Nov, 2015 - Comments: 3

The increasing cost of feature scaling is splintering the chip market, injecting uncertainty into a global supply chain that has been continually fine-tuned for decades. Those with deep enough resources and a clear need for density will likely follow Moore's Law, at least until 7nm. What comes after that will depend on a variety of factors ranging from available lithography—EUV, multi-bea... » read more

Pick A Number
By Ed Sperling - 24 Sep, 2015 - Comments: 0

For the past two years there was some mumbling that 16/14nm would be short-lived, and that 10nm would be the place that foundries would invest heavily. Now the buzz is that 10nm may be skipped entirely and the next node will be 7nm. After all, 10nm is really only a half-node. Or is it? The answer depends on who's defining 10nm. The 16/14nm node is based on a 20nm back-end-of-line process, un... » read more

Challenges At Advanced Nodes
By Ed Sperling - 09 Sep, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss finFETs, 22nm FD-SOI and how the how the market will segment over the next few years with Marie Semeria, CEO of [getentity id="22192" e_name="Leti"]; Patrick Soheili, vice president of product management and corporate development at [getentity id="22242" e_name="eSilicon"]; Paul Boudre, CEO of Soitec; and Subramani Kengeri, vice president of global ... » read more

Tech Talk: 10nm Patterning
By Brian Bailey - 20 Aug, 2015 - Comments: 0

David Abercrombie, advanced physical verification methodology program manager at Mentor Graphics, talks about triple and quadruple patterning after 20/16/14nm and what design teams need to understand to get this right. [youtube vid=7bjutPWakpw] » read more

The Great Imbalance
By Ed Sperling - 23 Jul, 2015 - Comments: 2

The number of options for chipmakers is growing while the number of chipmakers is shrinking. So what does this mean for the semiconductor industry? Short answer: No one is quite sure yet. But a lot more people are beginning to ask that question these days, including investors and analysts. There are a number of factors at play here. To begin with, there are more nodes to choose from than at ... » read more

The Fill Ecosystem Evolves Again
By Jeff Wilson - 23 Jul, 2015 - Comments: 0

Several years ago, we wrote about the ecosystem of fill, and how 20nm technology required a much tighter relationship between the foundry, designers and EDA vendors. While the players remain the same, there have been some interesting shifts in fill techniques and usage as designers move to even-smaller technologies. What continues with each node is the additional complexity of the design flo... » read more

Design Virtualization And Its Impact On SoC Design
By eSilicon - 27 May, 2015 - Comments: 0

At advanced technology nodes (40nm and below), the number of options that a system-on-chip (SoC) designer faces is exploding. Choosing the correct combination of these options can have a dramatic impact on the quality, performance, cost and schedule of the final SoC. Using conventional design methodologies, it is very difficult to know if the correct options have been chosen. There is simply ... » read more

← Older posts

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy