Trouble Ahead For IP industry?


[getkc id="106" kc_name="Power-aware design"] has risen from an afterthought to a primary design constraint for some design types. Initially it was smart phones and other battery operated devices. It has consistently expanded into additional areas including those plugged into the wall and those plugged into the grid. Some parts of the world are imposing restrictions on the power that a device c... » read more

TSMC: Rise of the “Phantom Node”


TSMC’s financial results for Q4 of 2014 and for the full year were announced in January with TSMC stating it again had achieved record sales and profits. The fourth quarter saw TSMC set records for revenue, earnings per share and cash balance. TSMC made bold predictions last year about 20nm revenue by Q4 2014, and it appears it has met them (see 28nm Powers TSMC Forward, Part Deux). TSMC repo... » read more

3D Effects At 20nm And Beyond


At the 20nm process node and below, attenuated phase shift masks (PSM) are used in the photolithography process, which results in approximately 70nm of topography. This now must be accounted for using 3D mask approximation. Aki Fujimura, CEO of [getentity id="22864" comment="D2S"], explained that in terms of [getkc id="80" comment="lithography"], where simulation-based technologies are used,... » read more

Low Power Trends Toward FinFET


My previous blog, Power Reduction Techniques, covered which low power techniques were applicable for various process nodes, from larger planar CMOS process technologies through finFET. The 16 and 14nm finFET-based process nodes are moving into production this year, and we are seeing many companies rapidly move their designs to finFET. In my last post, I noted some of the reasons why finFET is s... » read more

Darker Silicon


For the last several decades, integrated circuit manufacturers have focused their efforts on [getkc id="74" comment="Moore's Law"], increasing transistor density at constant cost. For much of that time, Dennard’s Law also held: As the dimensions of a device go down, so does power consumption. Smaller transistors ran faster, used less power, and cost less. As most readers already know, howe... » read more

Next Channel Materials?


Chipmakers are making a giant leap from planar transistors to [getkc id="185" kc_name="finFETs"]. Initially, [getentity id="22846" e_name="Intel"] moved into finFET production at 22nm and is now ramping up its second-generation finFETs at 14nm. And the other foundries will enter the finFET fray at 16nm/14nm. So what’s next? Chipmakers will likely extend the finFET architecture to both 10nm... » read more

Manufacturing Constraint Fears Grow


The semiconductor industry could become a victim of its own success. With so many semiconductors being consumed inside of cars, home electronics and industry, capacity shortages are beginning to surface in some areas. Foundries set rates depending upon a complex mix of process technology, equipment depreciation, customer demand and the need to push customers from one node the next depending ... » read more

What’s The Other Guy Doing?


Competition is generally a good thing. It improves service, promotes innovation, forces efficiencies and price cuts where necessary, and it ratchets up the pressure to bring products and services to market faster. Those who can't keep up usually lose market share, and eventually the business sector consolidates until something comes along to disrupt it. That cycle has been repeated in every ... » read more

Why Is My Device Better Than Yours?


Differentiation is becoming a big problem in the semiconductor industry with far-reaching implications that extend well beyond just chips. The debate over the future of [getkc id="74" comment="Moore's Law"] is well known, but it's just one element in a growing list that will make it much harder for chip companies, IP vendors and even software developers to stand out from the pack. And withou... » read more

Quantifying IP Entitlement For 14/16nm Technologies


The scaling benefits of [getkc id="74" comment="Moore"s Law"] are being seriously tested at 28nm. It is no longer a given that the cost per gate will go down at leading edge process nodes below 28nm, e.g., 20nm though 14nm. Rising design and manufacturing costs are contributing factors to this trend. Meanwhile, the competing trend of fewer but more complex [getkc id="81" comment="SoC"] (So... » read more

← Older posts Newer posts →