tag: 20nm

The Trouble With FinFETs
By Joanne Itow - 16 Aug, 2012 - Comments: 0

By Joanne Itow The industry’s quest to continue on the semiconductor roadmap defined by Moore’s Law has led to the adoption of a new transistor structure. Whether you call them finFETs, tri-gate or 3D transistors, building these new devices is difficult. But the technology is only half the challenge. In 2002, Chen Ming Hu* spoke at the Semico Summit. The title of his presentation was �... » read more

Double Patterning: Challenges And Possible Solutions In Parasitics Extraction
By David Abercrombie - 16 Aug, 2012 - Comments: 0

By Dusan Petranovic and David Abercrombie Double patterning (DP), as the simplest form of multi-patterning techniques, is receiving lots of attention right now. The need for double patterning techniques is driven by the physical limits of the dimensions that can be resolved with current light sources and lenses, as well as by the difficulties and delays in deploying next-generation lithography... » read more

Revisiting Moore’s Law
By Ed Sperling - 09 Aug, 2012 - Comments: 0

Moore’s Law was predicted to end at 1 micron. It was predicted to die off twice by Gordon Moore himself. And it has vacillated between 18 and 24 months on at least a couple of occasions since it was first introduced in 1965. From a technology perspective, there is no reason to assume it will ever die. It has gone from microns to nanometers and it can continue well into the picometer range.... » read more

Experts At The Table: Challenges At 20nm
By Ed Sperling - 09 Aug, 2012 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss the challenges at 20nm and beyond with Jean-Pierre Geronimi, special projects director at STMicroelectronics; Pete McCrorie, director of product marketing for silicon realization at Cadence; Carey Robertson, director of product marketing at Mentor Graphics; and Isadore Katz, president and CEO of CLK Design Automation. Wh... » read more

Investment Options
By Ed Sperling - 31 Jul, 2012 - Comments: 0

It's clear that something fundamental has changed in the semiconductor manufacturing industry. What's less clear is how this will play out over the long term. Intel's agreement to invest more than $4 billion in ASML to ensure the continued development of EUV and 450mm wafer technology is more than just a one-off deal. It's a very public recognition that the astronomical cost of design and ma... » read more

Routing Congestion Returns
By Ed Sperling - 26 Jul, 2012 - Comments: 0

By Ed Sperling Routing congestion has returned with a vengeance to SoC design, fueled by the advent of more third-party IP, more memory, a variety of new features, as well as the inability to scale wires at the same rate as transistors. This is certainly not a foreign concept for IC design. The markets for place and route tools were driven largely by the need to automate this kind of operat... » read more

Future Foundry Issues
By Ed Sperling - 13 Jul, 2012 - Comments: 0

Semiconductor Manufacturing & Design talks with Luigi Capodieci, fellow at GlobalFoundries, about EUV, the challenges at 20nm and beyond, and the future of the foundry model. [youtube vid=YXov4y0kpfU] » read more

28, 20nm Nodes Demand Advanced Power Management
By Ed Sperling - 12 Jul, 2012 - Comments: 0

By Ann Steffora Mutschler With the complexity of getting 28 and 20nm designs to reach desired yields with the desired power and performance on the shoulders of design teams, advanced power management techniques are a must. Sub-clock power gating, clock power gate structures, adaptive body bias and other techniques are making it possible. Sub-Clock Power Gating Far from a new techniqu... » read more

Experts At The Table: Pain Points
By Ed Sperling - 12 Jul, 2012 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down with Vinod Kariat, a Cadence fellow; Premal Buch, vice president of software engineering at Altera; Vic Kulkarni, general manager of Apache Design; Bernard Murphy, CTO at Atrenta, and Laurent Moll, CTO at Arteris. What follows are excerpts of that conversation. LPHP: Where will the pain points be going forward? Kariat: 20nm is... » read more

Leti Looks at Using Strain with FD-SOI for High-Perf Apps
By Various Writers - 29 Jun, 2012 - Comments: 0

The researchers at Leti working on FD-SOI have extremely deep expertise in it. One of the areas they've looked at is performance boosters. With the interest in FD-SOI rapidly increasing on the heels of the recent ST-GF announcement, their work becomes even more timely. A key Leti team wrote a summary of some recent strain work, which first appeared as part of the Advanced Substra... » read more

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