The Trouble With FinFETs

3D transistor technology is only half the challenge; the rest is the strain it puts on the foundry model.

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By Joanne Itow
The industry’s quest to continue on the semiconductor roadmap defined by Moore’s Law has led to the adoption of a new transistor structure. Whether you call them finFETs, tri-gate or 3D transistors, building these new devices is difficult. But the technology is only half the challenge.

In 2002, Chen Ming Hu* spoke at the Semico Summit. The title of his presentation was “The Future of Semiconductor Scaling.” In 2002, Hu pointed out that TSMC already had fabricated 35nm CMOS FinFET transistors on TSMC production tools and expected the technology to be scalable to 9nm. Ten years has elapsed and Intel is the first to run 22nm Ivy Bridge products using tri-gate technology. From a technical perspective, FinFETs are now proven to be executable in volume production. But how should we look at this from a market perspective?

When will the foundries be ready to ramp FinFET technology in volume production? And more importantly, when will foundry customers realistically be ready to fully utilize the technology? Until recently, the most advanced dedicated foundries were planning to introduce FinFETs on their 14nm technology. It appears that schedule has been accelerated. TSMC is talking about a 16nm transition node with FinFETs. GlobalFoundries just announced the development of ARM low-power processor designs for 20nm and finFET process technologies targeting SoCs including graphics processors. This doesn’t commit GlobalFoundries to finFETs at 20nm, but it does offer some options.

Semiconductor units continue to grow, and wafer demand increases right along with it. Any new technology that enables improved or new electronic applications should be implemented. Unfortunately, it’s not that easy. New consumer markets are cost-sensitive. The introduction of innovative technologies must take into consideration market competition, cost to volume, and opportune applications.

The following graph presents wafer demand assuming finFET adoption at 20nm versus 14nm. Although this graph depicts an “all-or-nothing” scenario, if finFETs are adopted by the industry at 22nm/20nm it could mean a significant difference in the total wafers used to produce finFET products.

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The following graph adds in a line comparing finFET adoption with the adoption of HKMG. Intel was also the first to implement HKMG at the 45nm node. GlobalFoundries and Samsung introduced HKMG at 32nm. TSMC began ramping HKMG with its 28nm production in 2011, almost four years after Intel.

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The smartphone and tablet markets continue to grow and the ultra-mobile PC market is beginning to take off. When the foundries transition to 20nm, the capacity ramp will have to be much larger than the ramp for HKMG at 32nm/28nm. Filling those market needs will be challenging. When 28nm was introduced at TSMC, customers could opt for a poly/SiOn gate stack versus the HKMG. That had a dampening effect on the volumes of HKMG wafers during the early ramp of 28nm. As companies begin to roll out 20nm products, once again there are a few options. Some companies may switch to finFETs. TSMC plans to stick with a bulk planar structure. As an alternative to bulk planar, there is also a fully depleted SOI option. Whether finFETs are introduced at 20nm, 16nm or 14nm, Semico believes their ramp will prove to be another test of the foundry model.

For additional data on wafer demand by product by technology, please visit Semico’s website for a current list of manufacturing studies.

*Chen Ming Hu is currently Distinguished Professor of Microelectronics at the University of California, Berkeley. At the time of his presentation at the Semico Summit in 2002, he was the Chief Technology Officer for TSMC.