tag: 3D-IC

The Next 5 Years Of Chip Technology
By Ed Sperling - 14 Mar, 2018 - Comments: 0

Semiconductor Engineering sat down to discuss the future of scaling, the impact of variation, and the introduction of new materials and technologies, with Rick Gottscho, CTO of Lam Research; Mark Dougherty, vice president of advanced module engineering at GlobalFoundries; David Shortt, technical fellow at KLA-Tencor; Gary Zhang, vice president of computational litho products at ASML; and Shay... » read more

Exponentials At The Edge
By Ed Sperling - 08 Mar, 2018 - Comments: 0

The age of portable communication has set off a scramble for devices that can achieve almost anything a desktop computer could handle even five years ago. But this is just the beginning. The big breakthrough with mobile devices was the ability to combine voice calls, text and eventually e-mail, providing the rudiments of a mobile office-all on a single charge of a battery that was light enou... » read more

New Issues In Advanced Packaging
By Ann Mutschler - 08 Mar, 2018 - Comments: 1

Advanced packaging is gaining in popularity as the cost and complexity of integrating everything onto a planar SoC becomes more difficult and costly at each new node, but ensuring that these packaged die function properly and yield sufficiently isn't so simple. There are a number of factors that are tilting more of the the semiconductor industry toward advanced [getkc id="27" kc_name="packag... » read more

Toward High-End Fan-Outs
By Ed Sperling - 05 Mar, 2018 - Comments: 1

Foundries and OSATs are working on more advanced fan-outs, including some with vertically stacked die inside the package, filling a middle ground between lower-cost fan-outs and systems in package on one side and 2.5D and 3D-ICs on the other. These new [getkc id="202" kc_name="fan-outs"] have denser interconnects than previous iterations, and in some cases they include multiple routing layer... » read more

New Thermal Issues Emerge
By Ann Mutschler - 12 Feb, 2018 - Comments: 0

Thermal monitoring is becoming more critical as gate density continues to increase at each new node and as chips are developed for safety critical markets such as automotive. This may sound counterintuitive because the whole point of device scaling is to increase gate density. But at 10/7 and 7/5nm, static current leakage is becoming a bigger issue, raising questions about how long [getkc id... » read more

What’s In The Package?
By Ed Sperling - 05 Feb, 2018 - Comments: 0

Putting a variety of chips or hardened IP blocks into a package rather than trying to cram them into a single chip continues to gain ground. But it's also creating its own set of issues around verifying and testing these devices. This problem is well understood inside of SoCs, where everything is integrated into a single die. And looked at from a 30,000-foot perspective, packaging is someth... » read more

Fan-Out Wars Begin
By Mark LaPedus - 05 Feb, 2018 - Comments: 3

Several packaging houses are developing the next wave of high-density fan-out packages for premium smartphones, but perhaps a bigger battle is brewing in the lower density fan-out arena. Amkor, ASE, STATS ChipPAC and others sell traditional low-density fan-out packages, although some new and competitive technologies are beginning to appear in the market. Low-density fan-out, or sometimes cal... » read more

Advanced Packaging Still Not So Simple
By Ed Sperling - 08 Jan, 2018 - Comments: 1

The promise of advanced packaging comes in multiple areas, but no single packaging approach addresses all of them. This is why there is still no clear winner in the packaging world. There are clear performance benefits, because the distance between two chips in a package can be significantly shorter than the distance that signals have to travel from one side of a die to another. Moreover, wi... » read more

Packaging Challenges For 2018
By Mark LaPedus - 08 Jan, 2018 - Comments: 0

The IC packaging market is projected to see steady growth this year, amid ongoing changes in the landscape. The outsourced semiconductor assembly and test ([getkc id="83" kc_name="OSAT"]) industry, which provides third-party packaging and test services, has been consolidating for some time. So while sales rising, the number of companies is falling. In late 2017, for example, [getentity id="2... » read more

Fan-Outs vs. TSVs
By Jeff Dorsch - 13 Dec, 2017 - Comments: 0

Two years ago, at the annual IMAPS conference on 2.5D and 3D chip packaging, the presentations were dominated by talk of fan-out wafer-level packaging. There was almost no talk of through-silicon vias, which previously had been heralded as vital to 2.5D and 3DIC packaging. Fast forward to this month's 3D Architectures for Heterogeneous Integration and Packaging conference in Burlingame, Cali... » read more

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