tag: 3D-IC

Packaging Tradeoffs More Complex Than Ever
By Ed Sperling - 24 May, 2012 - Comments: 0

By Ann Steffora Mutschler Driven by high-speed interfaces, the demand for TSVs and the complexities that new process nodes bring, older packaging technologies like wirebonding can’t keep up. The latest and greatest flip chip technologies offer much more flexibility, but at a cost. As such, the package plays a larger role than ever in determining system specifications because, depending o... » read more

New Power Standards Ahead
By Ed Sperling - 10 May, 2012 - Comments: 0

By Ed Sperling Standards groups are beginning to look at power and other physical effects much more seriously in the wake of the dueling power formats—UPF and CPF—that have caused angst across the design industry. To put it in perspective, when CPF and UPF were first introduced power was something of an afterthought in design. At 65nm it ceased to be something that could be dealt with l... » read more

The Next Steps
By Aveek Sarkar - 10 May, 2012 - Comments: 0

By Aveek Sarkar Remaining competitive in today’s semiconductor market means IC designers must meet performance, power and price targets for their design, regardless of the end application. Meeting these mutually conflicting goals requires enlisting the use of several architectural and design techniques, including three-dimensional (3D) or stacked-die architectures that can help meet perfo... » read more

Managing Complexity With Advanced Packaging
By Ed Sperling - 22 Mar, 2012 - Comments: 0

By Ann Steffora Mutschler Engineering teams across the globe continue to pound the process geometry treadmill to stay on the curve of Dr. Moore to achieve better speed or lower power or smaller die—and it all adds up to increased complexity in the design and packaging. However, with advanced forms of die stacking such as package-on-package, silicon-in-package, 2.5D silicon interposer techno... » read more

Off The Planar
By Ed Sperling - 15 Dec, 2011 - Comments: 0

By Pallab Chatterjee 3D devices, FinFETs and new memory technologies are not just a future direction anymore. They’re real. That became evident at this year’s IEDM conference, where the focus of a number of sessions was on modeling, failure and reliability models, as well as lower power supply operations for these devices. Because FinFETs are not standard 2D MOS devices, their use i... » read more

Something Old, Something Borrowed
By Ed Sperling - 11 Nov, 2011 - Comments: 0

The basic rule of SoC design is that it needs to be created relatively quickly, work as planned, and that it can be manufactured at a reasonable cost and with good yield ramp. That eliminates revolutionary changes on the technology side, limits the number of new materials, and relegates the most dramatic shifts to the business. That’s why most of the most far-reaching technology research i... » read more

Betting On Glass TSVs
By Ed Sperling - 22 Sep, 2011 - Comments: 0

By Ed Sperling There are two big issues when it comes to through-silicon vias. One involves cost. The second involves heat—in particular, how to get heat out of a stacked die and what the thermal coefficient of the TSV will be to make sure it expands at a rate consistent with the SoCs in a package. To address these issues, System-Level Design caught up with Rao Tummala, professor of elect... » read more

RF, MEMS, Photonics Driving 3D Stacking
By Ed Sperling - 28 Jul, 2011 - Comments: 0

By Pallab Chatterjee At Semicon West, a number of the key speakers and TechXPOTs were talking about current products being assembled and shipped with 3D technology. 3D die stacking is no longer a technology of the future. In fact it has been here for many years and has been used in millions, if not billions, of consumer, commercial and high-reliability designs. The two leading technologies ... » read more

3D Stacking: A Reality Check
By Ed Sperling - 28 Jul, 2011 - Comments: 0

By Ed Sperling The first 2.5D and 3D chips are expected to arrive next year, with the mainstream chip market expected to follow in 2013. While this trend already has seen its share of hype, stacked die—whether through a series of TSVs in true 3D or through an interposer layer in 2.5D—is as real as Moore’s Law. In fact, it’s a direct result of Moore’s Law. But unlike the progres... » read more

Solving Memory Subsystem Bottlenecks In 3D Stacks
By Ann Mutschler - 28 Jul, 2011 - Comments: 0

In today’s do-or-die market environment, many SOC makers strive to differentiate their product based upon the rate at which it performs processing. Closely coupled are power concerns that have led to dominance of a multi-core approach, while economic considerations have resulted in the dominance of the Unified Memory Architecture, where all the processors share access to external DRAM. Stacki... » read more

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