tag: 3D ICs

Impact of Clustering Methods On Partitioning Decisions For 3DICs (imec, Université libre de Bruxelles)
By Technical Paper Link - 28 Jul, 2023 - Comments: 0

A technical paper titled “Impact of gate-level clustering on automated system partitioning of 3D-ICs” was published by researchers at Université libre de Bruxelles and imec. Abstract: "When partitioning gate-level netlists using graphs, it is beneficial to cluster gates to reduce the order of the graph and preserve some characteristics of the circuit that the partitioning might degrade. ... » read more

Large-Scale Integration’s Future Depends On Modeling
By Karen Heyman - 27 Jul, 2023 - Comments: 0

VLSI is a term that conjures up images of a college textbook, but some of the concepts included in very large-scale integration remain relevant and continue to evolve, while others have fallen by the wayside. The portion of VLSI that remains most relevant for semiconductor industry is "integration," which is pushing well beyond the edges of a monolithic planar chip. But that expansion also i... » read more

Getting Rid Of Heat In Chips
By Brian Bailey - 20 Jul, 2023 - Comments: 1

Power consumed by semiconductors creates heat, which must be removed from the device, but how to do this efficiently is a growing challenge. Heat is the waste product of semiconductors. It is produced when power is dissipated in devices and along wires. Power is consumed when devices switch, meaning that it is dependent upon activity, and that power is constantly being wasted by imperfect de... » read more

RTL Restructuring Issues
By Ed Sperling - 18 Jul, 2023 - Comments: 0

Modification of modules in RTL is the last place in chip design where changes can be made relatively easily before they reach physical design, but it’s still as complicated as the design itself — and it becomes more difficult in 3D-ICs. Jim Schultz, product marketing manager for digital design implementation at Synopsys, talks about grouping and ungrouping, re-parenting, and breaking connec... » read more

Chip Design CEO Outlook
By Ed Sperling - 25 May, 2023 - Comments: 0

Semiconductor Engineering sat down with Joseph Sawicki, executive vice president for IC EDA at Siemens Digital Industries Software; John Kibarian, president and CEO of PDF Solutions; John Lee, general manager and vice president of Ansys' Semiconductor Business Unit; Niels Faché, vice president and general manager of PathWave Software Solutions at Keysight; Dean Drako, president and CEO of IC M... » read more

Optimizing Scan Test For Complex ICs
By Gregory Haley - 09 May, 2023 - Comments: 0

As chips become more heterogeneous with more integrated functionality, testing them presents increasing challenges — particularly for high-speed system-on-chip (SoC) designs with limited test pin availability. In addition, the complexity of emerging packages like 3D and chiplets necessitates comprehensive new solutions that can provide faster results at multiple stages in the silicon lifec... » read more

Big Changes Ahead For Chip Technology And Industry Dynamics
By Ed Sperling - 08 Feb, 2023 - Comments: 0

Semiconductor Engineering sat down to discuss the impact of customization and advanced packaging, and concerns about reliability and geopolitical rivalries with Martin van den Brink, president and CTO of ASML; Luc Van den Hove, CEO of imec; David Fried, vice president of computational products at Lam Research; and Ankur Gupta, vice president and general manager of the test group and lifecycle s... » read more

Multi-Die Integration
By Ed Sperling - 04 Jan, 2023 - Comments: 0

Putting multiple heterogeneous chips is the way forward for improved performance and more functionality, but it also brings a host of new challenges around partitioning, layout, and thermal. Michael Posner, senior director for die-to-die connectivity at Synopsys, talks about the advantages of 3D integration, why it’s finally going mainstream, and what’s needed in the EDA tools to make this ... » read more

Designing For Multiple Die
By Ann Mutschler - 21 Dec, 2022 - Comments: 1

Integrating multiple die or chiplets into a package is proving to be very different than putting them on the same die, where everything is developed at the same node using the same foundry process. As designs become more heterogeneous and disaggregated, they need to be modeled, properly floor-planned, verified, and debugged in the context of a system, rather than as individual components. Typi... » read more

The March Toward Chiplets
By Ed Sperling and Karen Heyman - 15 Dec, 2022 - Comments: 0

The days of monolithic chips developed at the most advanced process nodes are rapidly dwindling. Nearly everyone working at the leading edge of design is looking toward some type of advanced packaging using discrete heterogeneous components. The challenge now is how to shift the whole chip industry into this disaggregated model. It's going to take time, effort, as well as a substantial reali... » read more

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