Design IP

By Cadence - 01 Mar, 2023 - Comments: 0

Cadence is a leader in semiconductor IP addressing hyperscale computing, enterprise, data center, automotive, and artificial intelligence/machine learning (AI/ML) applications. Our IP are available in advanced-process nodes ranging from 28nm to 3nm—all silicon verified in leading-edge foundry processes. Our memory IP portfolio spans DDR, LPDDR, and GDDR. The Cadence® IP family for PCI Expres... » read more

On-Chip Power Distribution Modeling Becomes Essential Below 7nm

By Ann Mutschler - 16 Nov, 2022 - Comments: 0

Modeling power distribution in SoCs is becoming increasingly important at each new node and in 3D-ICs, where tolerances involving power are much tighter and any mistake can cause functional failures. At mature nodes, where there is more metal, power problems continue to be rare. But at advanced nodes, where chips are running at higher frequencies and still consuming the same or greater power... » read more

High-Tech: Innovation At The Speed of Light

By Ansys - 12 Jan, 2022 - Comments: 0

As connectivity, digitalization, and autonomy proliferate, the boundaries between industries are blurring at an unprecedented pace. Promising to unleash $3TN in global technology market spending, the new competitive battleground is to be found where the system electronics and semiconductor worlds collide: The 3D Integrated Circuit System-on-a-Chip. Winning demands a new design paradigm that ... » read more

Manufacturing Bits: Dec. 14

By Mark LaPedus - 14 Dec, 2021 - Comments: 0

3D-SOCs At this week’s IEEE International Electron Devices Meeting (IEDM), a plethora of companies, R&D organizations and universities presented papers on the latest and greatest technologies. One of the themes at IEDM is advanced packaging, a technology enables an IC vendor to boost the performance of a chip. Advanced forms of packaging also enables new 3D-like chip architectures. Fo... » read more

What’s Next For Transistors And Chiplets

By Mark LaPedus - 21 Oct, 2021 - Comments: 5

Sri Samavedam, senior vice president of CMOS Technologies at Imec, sat down with Semiconductor Engineering to talk about finFET scaling, gate-all-around transistors, interconnects, packaging, chiplets and 3D SoCs. What follows are excerpts of that discussion. SE: The semiconductor technology roadmap is moving in several different directions. We have traditional logic scaling, but packaging i... » read more

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Entities, people and technologies explored

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

Legacy Process Nodes Going Strong

The critical, and growing, significance of mature node chips and processes.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: 3D SoC

Design IP

On-Chip Power Distribution Modeling Becomes Essential Below 7nm

High-Tech: Innovation At The Speed of Light

Manufacturing Bits: Dec. 14

What’s Next For Transistors And Chiplets

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Knowledge Centers
Entities, people and technologies explored