tag: 3D

Litho Options For Panel Fan-out
By Mark LaPedus - 06 Nov, 2017 - Comments: 2

Several packaging houses are inching closer to production of panel-level fan-out packaging, a next-generation technology that promises to reduce the cost of today’s fan-out packages. In fact, ASE, Nepes, Samsung and others already have installed the equipment in their panel-level fan-out lines with production slated for 2018 or so. But behind the scenes, panel-level packaging houses contin... » read more

Managing Peak Power
By Ann Mutschler - 20 Sep, 2017 - Comments: 0

Peak power is becoming a serious design constraint across chips and entire electronic systems as more functionality is added into end devices and the compute and switching infrastructure needed to support them. The issues are a direct result of growing complexity in designs, fixed or shrinking power budgets, and the need to process more data more quickly. In mobile devices, the addition of m... » read more

What’s After 7nm?
By Ed Sperling - 14 Sep, 2017 - Comments: 1

The rollout of 10/7nm was a long time coming, and for good reason. It's hard stuff, and chipmakers have to be ready to take a giant step forward with new processes, tools, and to deal with a slew of physical effects that no longer can be handled by just guard-banding a design. The big question is what's next, when it will happen, and how much it will cost. Preparing for the next process node... » read more

Executive Insight: Lip-Bu Tan
By Ed Sperling - 06 Sep, 2017 - Comments: 2

Semiconductor Engineering sat down with Lip-Bu Tan, president and CEO of [getentity id="22032" e_name="Cadence"], to discuss disruptions and changes in the semiconductor industry, from machine learning and advance packaging to tools and business. What follows are excerpts of that conversation. SE: What do you see as the next big thing? Tan: Unlike mobility or cell phones, or PCs before th... » read more

Is Design Innovation Slowing?
By Brian Bailey - 10 Aug, 2017 - Comments: 0

Paul Teich, principal analyst for Tirias Research, gave a provocative talk at the recent DAC conference entitled, "Is Integration Leaving Less Room for Design Innovation?" The answer isn't as simple as the question might suggest. "Integration used to be a driver for increasing the functionality of silicon," Teich said. "Increasingly, it will be used to incorporate more features of an entire ... » read more

Challenges For Future Fan-Outs
By Mark LaPedus - 07 Jul, 2017 - Comments: 1

The fan-out wafer-level packaging market is heating up. At the high end, for example, several packaging houses are developing new fan-out packages that could reach a new milestone and hit or break the magic 1µm line/space barrier. But the technology presents some challenges, as it may require more expensive process flows and equipment like lithography. Fig. 1: Redistribution layers. Source: L... » read more

Deep Learning Robust Grasps with Synthetic Point Clouds & Analytic Grasp Metrics (UC Berkeley)
By Technical Paper Link - 28 Jun, 2017 - Comments: 0

Source: The research was the work of Jeffrey Mahler, Jacky Liang, Sherdil Niyaz, Michael Laskey, Richard Doan, Xinyu Liu, Juan Aparicio Ojea, and Ken Goldberg with support from the AUTOLAB team at UC Berkeley. Nimble-fingered robots enabled by deep learning Grabbing awkwardly shaped items that humans regularly pick up daily is not so easy for robots, as they don’t know where to apply grip... » read more

Ultra-Thin Substrate Assembly Challenges For Advanced Flip Chip Package
By STATS ChipPAC - 08 May, 2017 - Comments: 0

Advanced semiconductor packaging requirements for higher and faster performance in a thinner and smaller form factor continues to grow for mobile, network and consumer devices. While the increase in device input/output (I/O) count is driven by the famous “Moore’s Law”, the packaging industry is experiencing opposing trends for more complex packaging solutions while the expected cost targe... » read more

Design For Silicon Success At 7nm
By Annapoorna Krishnaswamy - 01 May, 2017 - Comments: 0

Next-generation automotive, mobile and high-performance computing applications demand the use of 7nm SoCs to deliver greater functionality and higher performance at much lower power. According to Gartner, when compared to 16nm/14nm technology, 7nm offers 35% speed improvement, 65% less power, and 3.3X density improvement. Hence, despite a whopping cost of $271M — per Gartner's estimate — to... » read more

System-Level Testing
By Astronics - 10 Apr, 2017 - Comments: 0

This white paper on system-level testing for semiconductors. Covering the history and trends of system-level test for semiconductors, this solution brief discusses: The increasing complexities of testing advanced semiconductor integrated devices across a span of applications: automotive, mobile computing, wearables, and more; Semiconductor trends driving necessary shifts in testing method... » read more

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