tag: 3D

Stacked Die Changes
By Ed Sperling - 21 Sep, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss advanced packaging with David Pan, associate professor in the department of electrical and computer engineering at the University of Texas; Max Min, senior technical manager at [getentity id="22865" e_name="Samsung"]; John Hunt, senior director of engineering at ASE; and Sitaram Arkalgud, vice president of 3D portfolio and technologies at Invensas. ... » read more

Stacked Die Changes
By Ed Sperling - 15 Sep, 2016 - Comments: 1

Semiconductor Engineering sat down to discuss advanced packaging with David Pan, associate professor in the department of electrical and computer engineering at the University of Texas; Max Min, senior technical manager at [getentity id="22865" e_name="Samsung"]; John Hunt, senior director of engineering at ASE; and Sitaram Arkalgud, vice president of 3D portfolio and technologies at Invensas. ... » read more

Manufacturing Bits: April 12
By Mark LaPedus - 12 Apr, 2016 - Comments: 0

Ink FETs The University of Pennsylvania has developed a new way to make chips by using nanocrystal inks. The devices, dubbed nanocrystal field-effect transistors (FETs), could be used one day to develop chips for flexible and wearable applications In the lab, researchers devised spherical nanoscale particles. These particles, which have electrical characteristics, were dispersed in a liquid... » read more

The Week In Review: Manufacturing
By Mark LaPedus - 24 Dec, 2015 - Comments: 0

South Korea’s SK Hynix led the initial charge in the development of High Bandwidth Memory (HBM), a 3D DRAM technology based on a memory stack and through-silicon vias (TSVs). SK Hynix has been shipping HBM parts in the market. Now, SK Hynix and Samsung are readying the next version of the technology, dubbed High Bandwidth Memory 2 or HMB2, according to a report from The Electronic Times of So... » read more

Memory Choices Grow
By Ed Sperling - 24 Nov, 2015 - Comments: 1

Memory is becoming one of the starting points for SoC architectures, evolving from a basic checklist item that was almost always in the shadow of improving processor performance or lowering the overall power budget. In conjunction with that shift, chipmakers must now grapple with many more front-end decisions about placement, memory type and access prioritization. There are plenty of rules ... » read more

Why Packaging Matters
By Ed Sperling - 19 Nov, 2015 - Comments: 1

The semiconductor package is changing. What was until very recently considered an afterthought is now becoming a key part of the design process at all major chipmakers, and a critical factor in the extension of Moore's Law. This is a sharp reversal of what was almost universally an afterthought in planar silicon design and manufacturing. Rarely was the package an integral part of the archite... » read more

Packaging Wars Ahead
By Ed Sperling - 19 Nov, 2015 - Comments: 0

There has been much talk about semiconductor industry consolidation, but the shift into advanced packaging could have more far-reaching effects than all the mega-deals so far. Packaging is big business. Yole Développement has pinned the market at $30 billion, but that's only a thin slice of the pie that's in play. Companies that win the packaging deals also have a good shot of winning the m... » read more

Increasing Challenges At Advanced Nodes
By Ed Sperling - 22 Oct, 2015 - Comments: 1

Gary Patton, chief technology officer at GlobalFoundries, sat down with Semiconductor Engineering to talk about new materials, stacked die, how far FD-SOI can be extended, and new directions for interconnects and transistors. What follows are excerpts of that conversation. SE: Where do you see problems at future nodes? Patton: At the device level, we have to be able to pattern these thing... » read more

First Look: 5nm
By Ann Mutschler - 15 Oct, 2015 - Comments: 3

By the time the 5nm semiconductor manufacturing process node reaches mass production readiness, the hurdles and challenges will no longer be open for discussion. But as of this moment, some of them seem almost insurmountable, raising new questions about the continued viability of Moore's Law. There has been much written about the end of [getkc id="74" comment="Moore's Law"] for nearly two de... » read more

Raise A Fence, Dig A Tunnel, Build A Bridge
By Ed Sperling - 17 Sep, 2015 - Comments: 0

There are three main options for chipmakers over the course of the next decade. Which option they choose depends upon their individual needs, talents, and how much and what kind of differentiation they believe will matter to them. The options roughly fall into three categories—fence, bridge or tunnel. The fence option Rather than changing anything, the entire ecosystem can stick to wha... » read more

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