tag: 5nm

7nm Lithography Choices
By Mark LaPedus - 07 Mar, 2016 - Comments: 2

Chipmakers are ramping up their 16nm/14nm logic processes, with 10nm expected to move into early production later this year. Barring a major breakthrough in lithography, chipmakers are using today’s 193nm immersion and multiple patterning for both 16/14nm and 10nm. Now, chipmakers are focusing on the lithography options for 7nm. For this, they hope to use a combination of two technologies ... » read more

Industry Road Map Under Construction
By Ed Sperling - 21 Jan, 2016 - Comments: 0

While most engineers think in terms of PPA—the classic power, performance and area tradeoffs—their bosses tend to see the world in terms of risk vs. opportunity. Until 22nm, these two objectives moved forward at roughly the same pace, despite the growing technical challenges of fitting more functionality into an SoC. Much has changed since then, and even more will change over the next f... » read more

5nm Fab Challenges
By Mark LaPedus - 21 Jan, 2016 - Comments: 2

At a recent event, Intel presented a paper that generated sparks and fueled speculation regarding the future direction of the leading-edge IC industry. The company described a next-generation transistor called the nanowire FET, which is a finFET turned on its side with a gate wrapped around it. Intel’s nanowire FET, sometimes called a gate-all-around FET, is said to meet the device require... » read more

Predictions For 2016: Semiconductors, Manufacturing And Design
By Brian Bailey - 21 Jan, 2016 - Comments: 0

Seventeen companies sent in their predictions for this year with some of them sending predictions from several people. This is in addition to the CEO predictions that were recently published. That is a fine crop of views for the coming year, especially since they know that they will be held accountable for their views and this year, just like the last, they will have to answer for them. We beli... » read more

Will 5nm Happen?
By Mark LaPedus - 20 Jan, 2016 - Comments: 7

Chipmakers are ramping up their 16/14nm finFET processes, with 10nm finFETs expected to ship sometime in late 2016 or early 2017. So what’s next? The foundries can see a path to extend the finFET transistor to 7nm, but the next node, 5nm, is far from certain and may never happen. Indeed, there are several technical and economic challenges at 5nm. And even if 5nm happens, only a few compani... » read more

Reflections On 2015
By Brian Bailey - 10 Dec, 2015 - Comments: 0

It is easy to make predictions, but few people can make them with any degree of accuracy. Most of the time, those predictions are forgotten by the end of the year and there is no one to do a tally of who holds more credibility for next year. Not so with Semiconductor Engineering. We like to hold people's feet to the fire, but while the "Pants-On-Fire" meter may be applicable to politicians, we ... » read more

Ecosystem Vs. Ecosystem
By Ed Sperling - 12 Nov, 2015 - Comments: 0

The massive consolidation that has been underway over the past couple years is about to slow down. Interest rates are expected to increase in the very near future—the Fed has been dropping hints about this for months—ending the era of cheap capital. The cost of borrowing already is creeping up in anticipation of this, and it's happening globally because money lending is a global industry. ... » read more

Increasing Challenges At Advanced Nodes
By Ed Sperling - 22 Oct, 2015 - Comments: 1

Gary Patton, chief technology officer at GlobalFoundries, sat down with Semiconductor Engineering to talk about new materials, stacked die, how far FD-SOI can be extended, and new directions for interconnects and transistors. What follows are excerpts of that conversation. SE: Where do you see problems at future nodes? Patton: At the device level, we have to be able to pattern these thing... » read more

Will The Chip Work?
By Ed Sperling - 19 Oct, 2015 - Comments: 1

IP is getting better, but the challenges of integrating it are getting worse. As the number of IP blocks in SoCs increases at each new process node, so does the difficulty of making them all work together. In some cases, this can mean extra code and a slight performance hit on power and performance. In other cases, it may require more drastic measures, ranging from a re-spin to a new archite... » read more

Power Requires Holistic Perspective
By Ann Mutschler - 15 Oct, 2015 - Comments: 0

With the move to smaller manufacturing nodes, power must be looked at from a holistic perspective. Instead of just optimizing a device or devising next generation power gating, power must be considered in the context of the whole system, Aveek Sarkar, vice president of product engineering and support at Ansys/Apache mentioned during a recent discussion about 5nm. In fact, he said, this c... » read more

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