Variation’s Long Tentacles


Today, most design engineers don't pay much attention to variation. It's generally considered to be a manufacturing problem. Even within the fab, various job functions are segmented enough that variation in one part of the process, such as the photomask shop, doesn't necessarily come to the attention of the people doing deposition and etch or those polishing the wafers. But increasingly, ... » read more

The Data Deluge


Lip-Bu Tan, president and CEO of Cadence, sat down with Semiconductor Engineering to discuss the intersection of big data and technology, from the data center to the edge and vertical markets such as automotive. What follows are excerpts of that conversation. SE: What are the biggest changes you've seen over the past year? Tan: We are moving quickly toward data-driven economics. There... » read more

Power Issues Rising For New Applications


Managing power in chips is becoming more difficult across a wide range of applications and process nodes, forcing chipmakers and systems companies to rethink their power strategies and address problems much earlier than in the past. While power has long been a major focus in the mobile space, power-related issues now are spreading well beyond phones and laptop computers. There are several re... » read more

Boosting Analog Reliability


Aveek Sarkar, vice president of Synopsys’ Custom Compiler Group, talks about challenges with complex design rules, rigid design methodologies, and the gap between pre-layout and post-layout simulation at finFET nodes. https://youtu.be/JRYlYJ31LLw » read more

Tightening Margins On Heat


Stephen Crosher, CEO of Moortec, talks with Semiconductor Engineering about the impact of more accurate measurements on power, performance and reliability of designs from 40nm all the way down to 3nm. https://youtu.be/VnX-TiaMVmI » read more

Reducing Advanced Packaging Costs


Semiconductor Engineering sat down with Chenglin Liu, director of package engineering at Marvell; John Hunt, senior director of engineering at ASE; Eric Tosaya, senior director of package manufacturing at eSilicon; and Juan Rey, vice president of engineering for Calibre at Mentor, a Siemens Business. What follows are excerpts of that discussion, which was held in front of a live audience at MEP... » read more

FD-SOI At The Edge


Semiconductor Engineering sat down to discuss changes in the FD-SOI world and what's behind them, with James Lamb, deputy CTO for advanced semiconductor manufacturing and corporate technical fellow at Brewer Science; Giorgio Cesana, director of technical marketing at STMicroelectronics; Olivier Vatel, senior vice president and CTO at Screen Semiconductor Solutions; and Carlos Mazure, CTO at Soi... » read more

What’s the Right Path For Scaling?


The growing challenges of traditional chip scaling at advanced nodes are prompting the industry to take a harder look at different options for future devices. Scaling is still on the list, with the industry laying plans for 5nm and beyond. But less conventional approaches are becoming more viable and gaining traction, as well, including advanced packaging and in-memory computing. Some option... » read more

Top Stories For 2018


Each year, I look back to see what articles people like to read. The first thing that has amazed me each year at Semiconductor Engineering is that what should be a strong bias towards articles published early in the year never seems to play out. The same is true this year. More than half of the top articles were published after July. The second thing that remains constant is that people love... » read more

Will AI Drive Scaling Forward?


The almost ubiquitous rollout of AI and its offshoots—machine learning, deep learning, neural nets of all types—will require significantly more processing power as the amount of data that needs to be processed continues to grow by orders of magnitude. What isn't clear yet is how that will affect semiconductor manufacturing or how quickly that might happen. AI is more than the latest buz... » read more

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