tag: 7nm

Next EUV Issue: Mask 3D Effects
By Mark LaPedus - 25 Apr, 2018 - Comments: 6

As extreme ultraviolet (EUV) lithography moves closer to production, the industry is paying more attention to a problematic phenomenon called mask 3D effects. Mask 3D effects involve the photomask for EUV. In simple terms, a chipmaker designs an IC, which is translated from a file format into a photomask. The mask is a master template for a given IC design. It is placed in a lithography scan... » read more

AI Accelerating Discovery
By Joanne Itow - 25 Apr, 2018 - Comments: 0

In early April 2018, the Materials Research Society held their spring meeting and exhibit at the Phoenix, Arizona convention center. With more than 110 symposium presentations, it was difficult to select which sessions to attend. But one forum caught my eye, “AI for Materials Development”. These days AI seems to be everywhere. As we all speculate about the impact of AI on autonomous driv... » read more

IP Issues At 10/7nm
By Ranjit Adhikary - 23 Apr, 2018 - Comments: 0

For years chip makers have been demanding more options to assist them in getting silicon to market faster. As of 2018, there are now so many possibilities for chip makers that engineering teams of all types are having trouble wading through all the possibilities. To make matters worse, many of today’s choices now come with unexpected and often unwanted caveats. At the most advanced nodes... » read more

Mashup At 7nm
By Ed Sperling - 19 Apr, 2018 - Comments: 0

The merger of two standards organizations typically falls well below the radar of most engineers, but folding the ESD Alliance (formerly known as the EDA Consortium) into SEMI is a different kind of deal. Ever since the introduction of finFETs and multiple patterning, EDA tools have become an integral part of the development of new manufacturing processes. Without those tools, there is no po... » read more

Design Rule Complexity Rising
By Ed Sperling - 19 Apr, 2018 - Comments: 0

Variation, edge placement error, and a variety of other issues at new process geometries are forcing chipmakers and EDA vendors to confront a growing volume of increasingly complex, and sometimes interconnected design rules to ensure chips are manufacturable. The number of rules has increased to the point where it's impossible to manually keep track of all of them, and that has led to new pr... » read more

Searching For EUV Defects
By Mark LaPedus - 19 Apr, 2018 - Comments: 1

Chipmakers hope to insert extreme ultraviolet (EUV) lithography at 7nm and/or 5nm, but several challenges need to be solved before this oft-delayed technology can be used in production. One lingering issue that is becoming more worrisome is how to find defects caused by [gettech id="31045" comment="EUV"] processes. These processes can cause random variations, also known as stochastic effects... » read more

Architecture, Materials And Software
By Ed Sperling - 12 Apr, 2018 - Comments: 0

AI, machine learning and autonomous vehicles will require massive improvements in performance, at the same power consumption level (or better), over today's chips. But it's obvious that the usual approach of shrinking features to improve power/performance isn't going to be sufficient. Scaling will certainly help, particularly on the logic side. More transistors are needed to process a huge i... » read more

Get Ready For Integrated Silicon Photonics
By Brian Bailey - 12 Apr, 2018 - Comments: 1

Long-haul communications and data centers are huge buyers of photonics components, and that is leading to rapid advances in the technology and opening new markets and opportunities. The industry has to adapt to meet the demands being placed on it and solve the bottlenecks in the design, development and fabrication of integrated silicon photonics. "Look at the networking bandwidth used across... » read more

Tech Talk: 7/5/3nm Signoff
By Ed Sperling - 12 Apr, 2018 - Comments: 0

Anand Raman, director of technical marketing at Helic, explains what's needed to improve confidence in designs at the most advanced process nodes. https://youtu.be/2O2pbMJSta4 » read more

Choosing The Right Interconnect
By Ed Sperling - 09 Apr, 2018 - Comments: 3

Efforts to zero in on cheaper advanced packaging approaches that can speed time to market are being sidetracked by a dizzying number of choices. At the center of this frenzy of activity is the [getkc id="36" kc_name="interconnect"]. Current options range from organic, silicon and glass interposers, to bridges that span different die at multiple levels. There also are various fan-out approach... » read more

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