22nm Process War Begins

By Mark LaPedus - 23 Apr, 2017 - Comments: 1

Many foundry customers at the 28nm node and above are developing new chips and are exploring the idea of migrating to 16nm/14nm and beyond. But for the most part, those companies are stuck because they can’t afford the soaring IC design costs at advanced nodes. Seeking to satisfy a potential gap in the market, [getentity id="22819" comment="GlobalFoundries"], [getentity id="22846" e_name="... » read more

Inside Next-Gen Transistors

By Mark LaPedus - 20 Apr, 2017 - Comments: 0

David Fried, chief technology officer at [getentity id="22210" e_name="Coventor"], sat down with Semiconductor Engineering to discuss the IC industry, China, scaling, transistors and process technology. What follows are excerpts of that conversation. SE: In a recent roundtable discussion you talked about some of the big challenges facing the IC industry. One of your big concerns involves th... » read more

Moore’s Law: A Status Report

By Ed Sperling - 20 Apr, 2017 - Comments: 3

Moore's Law has been synonymous with "smaller, faster, cheaper" for the past 52 years, but increasingly it is viewed as just one of a number of options—some competing, some complementary—as the chip industry begins zeroing in on specific market needs. This does not make [getkc id="74" comment="Moore's Law"] any less relevant. The number of companies racing from 16/14nm to 7nm is higher t... » read more

Impact Of Rising SoC Design Costs On Innovation

By Rich Wawrzyniak - 20 Apr, 2017 - Comments: 0

If there is one truism in the semiconductor market, it is that rising costs will impact unit demand at some point if they continue long enough. The subject of this blog deals not with device ASPs; but rather with rising SoC design costs, and their effect on the number of designs at the advanced nodes. Even though the mechanism governing each set of numbers is different (device ASPs vs. design c... » read more

Managing Voltage Drop At 10/7nm

By Ann Mutschler - 13 Apr, 2017 - Comments: 0

Power integrity is becoming a bigger problem at 10/7nm because existing tools such as static analysis no longer are sufficient. Power integrity is a function of static and dynamic voltage drop in the power delivery network. And until recently, static analysis did an effective job in measuring the overall robustness of PDN connectivity. As such, it is a proxy for PDN strength. The problem is ... » read more

Inside Lithography And Masks

By Mark LaPedus - 05 Apr, 2017 - Comments: 3

Semiconductor Engineering sat down to discuss lithography and photomask technologies with Gregory McIntyre, director of the Advanced Patterning Department at [getentity id="22217" e_name="Imec"]; Harry Levinson, senior fellow and senior director of technology research at [getentity id="22819" comment="GlobalFoundries"]; David Fried, chief technology officer at [getentity id="22210" e_name="Cove... » read more

Biz Talk: ASICs

By Ed Sperling - 27 Mar, 2017 - Comments: 0

eSilicon CEO [getperson id="11145" comment="Jack Harding"] talks about the future of scaling, advanced packaging, the next big things—automotive, deep learning and virtual reality—and the need for security. [youtube vid=leO8gABABqk] Related Stories Executive Insight: Jack Harding (Aug 2016) eSilicon’s CEO looks at industry consolidation, competition, China’s impact, an... » read more

Patterning Problems Pile Up

By Mark LaPedus - 20 Mar, 2017 - Comments: 4

Chipmakers are ramping up 16nm/14nm finFET processes, with 10nm and 7nm now moving into early production. But at 10nm and beyond, chipmakers are running into a new set of problems. While shrinking feature sizes of a device down to 10nm, 7nm, 5nm and perhaps beyond is possible using current and future fab equipment, there doesn't seem to be a simple way to solve the edge placement error (EPE)... » read more

Playing With Chip Volumes

By Ed Sperling - 16 Mar, 2017 - Comments: 0

The overall market for semiconductors continues to grow, but the number of applications that will generate enormous volumes continues to shrink. In theory, this is good for the overall semiconductor industry, but it raises important questions about where R&D dollars will go in the future. The fundamental problem is that the semiconductor business is a volume business for one or two markets. ... » read more

Following Multiple Patterns

By Mark LaPedus - 16 Mar, 2017 - Comments: 2

The lithography market is in flux. Today, chipmakers plan to extend today’s 193nm immersion lithography and multi-patterning to at least 10nm and 7nm. For the most critical layers, though, it’s unclear if optical lithography can extend beyond 7nm. For that reason, chipmakers hope to insert extreme ultraviolet (EUV) lithography at 7nm and/or 5nm. To get a handle on the state of patterning, S... » read more

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tag: 7nm

22nm Process War Begins

Inside Next-Gen Transistors

Moore’s Law: A Status Report

Impact Of Rising SoC Design Costs On Innovation

Managing Voltage Drop At 10/7nm

Inside Lithography And Masks

Biz Talk: ASICs

Patterning Problems Pile Up

Playing With Chip Volumes

Following Multiple Patterns

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