Going On the Edge

By Mark LaPedus - 27 Jan, 2020 - Comments: 3

Emmanuel Sabonnadière, chief executive of Leti, sat down with Semiconductor Engineering to talk about artificial intelligence (AI), edge computing and chip technologies. What follows are excerpts of that conversation. SE: Where is AI going in the future? Sabonnadière: I am a strong believer that edge AI will change our lives. Today’s microelectronics are organized with 80% of things i... » read more

Finding Defects In EUV Masks

By Mark LaPedus - 23 Jan, 2020 - Comments: 0

Extreme ultraviolet (EUV) lithography is finally in production at advanced nodes, but there are still several challenges with the technology, such as EUV mask defects. Defects are unwanted deviations in chips, which can impact yield and performance. They can crop up during the chip manufacturing process, including the production of a mask or photomask, sometimes called a reticle. Fortunately... » read more

Analog: Avoid Or Embrace?

By Brian Bailey - 16 Jan, 2020 - Comments: 0

We live in an analog world, but digital processing has proven quicker, cheaper and easier. Moving digital data around is only possible while the physics of wires can be safely abstracted away enough to provide reliable communications. As soon as a signal passes off-chip, the analog domain reasserts control for modern systems. Each of those transitions requires a data converter. The usage ... » read more

Using Static Analysis For Functional Safety

By Ed Sperling - 15 Jan, 2020 - Comments: 0

Fadi Maamari, group director for R&D at Synopsys, explains why static analysis is suddenly in demand in auto chip design, how it can help to choose the best implementation of functional safety approaches, and where it fits into the design flow. » read more

Interdependencies Complicate IC Power Grid Design

By Ann Mutschler - 12 Dec, 2019 - Comments: 0

Creating the right power grid is a growing problem in leading-edge chips. IP and SoC providers are spending a considerable amount of time defining the architecture of logic libraries in order to enable different power grids to satisfy the needs of different market segments. The end of Dennard scaling is one of the reasons for the increased focus. With the move to smaller nodes, the amount of... » read more

Multi-Patterning EUV Vs. High-NA EUV

By Mark LaPedus - 04 Dec, 2019 - Comments: 4

Foundries are finally in production with EUV lithography at 7nm, but chip customers must now decide whether to implement their next designs using EUV-based multiple patterning at 5nm/3nm or wait for a new single-patterning EUV system at 3nm and beyond. This scenario revolves around ASML’s current extreme ultraviolet (EUV) lithography tool (NXE:3400C) versus a completely new EUV system with... » read more

Designing In 4D

By Ed Sperling - 26 Nov, 2019 - Comments: 0

The chip design world is no longer flat or static, and increasingly it's no longer standardized. Until 16/14nm, most design engineers viewed the world in two dimensions. Circuits were laid out along x and y axes, and everything was packed in between those two borders. The biggest problems were that nothing printed as neatly as the blueprint suggested, and current leaked out of two-dimension... » read more

Making Random Variation Less Random

By Ed Sperling - 21 Oct, 2019 - Comments: 0

The economics for random variation are changing, particularly at advanced nodes and in complex packaging schemes. Random variation always will exist in semiconductor manufacturing processes, but much of what is called random has a traceable root cause. The reason it is classified as random is that it is expensive to track down all of the various quirks in a complex manufacturing process or i... » read more

Week In Review: Manufacturing, Test

By Mark LaPedus - 18 Oct, 2019 - Comments: 0

Chipmakers The semiconductor capital spending race continues to escalate in the leading-edge logic space. Intel and Samsung have separately announced big capital spending plans in 2019. Intel’s latest CapEx budget is $15.5 billion in 2019, while Samsung’s CapEx is slated for $16.204 billion for the year, according to KeyBanc Capital Markets. Now, TSMC is raising the stakes. TSMC this... » read more

Mask Making Issues With EUV

By Mark LaPedus - 17 Oct, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss lithography and photomask trends with Bryan Kasprowicz, director of technology and strategy and a distinguished member of the technical staff at Photronics; Thomas Scheruebl, director of strategic business development and product strategy at Zeiss; Noriaki Nakayamada, senior technologist at NuFlare; and Aki Fujimura, chief executive of D2S. What fol... » read more

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Knowledge Centers
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