Slow Progress On Generative EDA


Progress is being made in generative EDA, but the lack of training data remains the biggest problem. Some areas are finding ways around this. Generative AI, driven by large language models (LLMs), stormed into the world just two years ago, and since then has worked its way into almost every aspect of our lives. Some people love it, others hate it, and some even give dire warnings about machi... » read more

How AI Is Transforming System Design


Experts At The Table: ChatGPT and other LLMs have attracted most of the attention in recent years, but other forms of AI have long been incorporated into design workflows. The technology has become so common that many designers may not even realize it’s a part of the tools they use every day. But its adoption is spreading deeper into tools and methodologies. Semiconductor Engineering sat down... » read more

GenAI + Semiconductors + Humanity


Silicon Catalyst held its 2024 Semiconductor Industry Forum in Mountain View, CA, at the Computer History Museum on November 13th. Richard Curtin, managing partner for Si Catalyst, opened the event by thanking David House, vice chair of the Board at the Computer History Museum and creator of the 4004 processor, and the CHM staff for hosting the event. Richard talked about the start of se... » read more

Small Language Models: A Solution To Language Model Deployment At The Edge?


While Large Language Models (LLMs) like GPT-3 and GPT-4 have quickly become synonymous with AI, LLM mass deployments in both training and inference applications have, to date, been predominately cloud-based. This is primarily due to the sheer size of the models; the resulting processing and memory requirements often overwhelm the capabilities of edge-based systems. While the efficiency of Exped... » read more

To (B)atch Or Not To (B)atch?


When evaluating benchmark results for AI/ML processing solutions, it is very helpful to remember Shakespeare’s Hamlet, and the famous line: “To be, or not to be.” Except in this case the “B” stands for Batched. Batch size matters There are two different ways in which a machine learning inference workload can be used in a system. A particular ML graph can be used one time, preced... » read more

AI’s Ability To Deliver Breakthroughs Across Semiconductor Design And Manufacturing


AI holds great promise for our industry. It will help close the divide between design, manufacturing and test that is required to effectively produce today’s most advanced hybrid devices. One way to look at the potential impact of AI in the semiconductor industry is to realize that it is more and more driven by software engineering. When designing a chip, it’s essentially like writing... » read more

Yield Management Embraces Expanding Role


Competitive pressures, shrinking time-to-market windows, and increased customization are collectively changing the dynamics and demands for yield management systems, shifting left from the fab to the design flow and right to assembly, packaging, and in-field analysis. The basic role of yield management systems is still expediting new product introductions, reducing scrap, and delivering grea... » read more

Scaling Performance In AI Systems


Improving performance in AI designs involves the usual tradeoffs in power and performance, but achieving a good balance is becoming much more challenging. There is more data to process, new heterogeneous architectures to contend with, and much higher utilization rates. Andy Nightingale, vice president of product management and marketing at Arteris, talks about where the bottlenecks are, how to ... » read more

Why 40G UCIe IP?


AI applications are bringing new challenges to the semiconductor industry. There is an increased demand for greater bandwidth, especially for compute and networking applications to support the high data processing required by deep learning and machine learning algorithms. The requirements for these AI applications are different for die-to-die interfaces. Let’s take 100Tb networking switches a... » read more

Reducing SoC Power With NoCs And Caches


Today’s system-on-chip (SoC) designs face significant challenges with respect to managing and minimizing power consumption while maintaining high performance and scalability. Network-on-chip (NoC) interconnects coupled with innovative cache memories can address these competing requirements. Traditional NoCs SoCs consist of IP blocks that need to be connected. Early SoCs used bus-based archi... » read more

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