Challenges In Printed And Disposable Chips

By Susan Rambo And Ed Sperling - 05 Mar, 2020 - Comments: 0

Printing inexpensive chips using technology developed for newspapers and magazines is gaining traction across a wide range of applications, from photovoltaic cells to sensors on a flexible substrate. But it's also adding a slew of new challenges that are unique to this approach. The world of flexible hybrid electronics (FHE) — printing integrated circuits on or attaching thin IC chips to a... » read more

Blog Review: March 4

By Jesse Allen - 04 Mar, 2020 - Comments: 0

Mentor's Shivani Joshi provides a primer on design rule checks and how they can help flag potential issues in PCB design. Synopsys' Taylor Armerding argues that while better IoT security requires a change in consumer culture and habits, manufacturers and government should be doing more as well. Cadence's Johnas Street chats with several colleagues about what Black History Month means to t... » read more

3nm: Blurring Lines Between SoCs, PCBs And Packages

By Ann Mutschler - 02 Mar, 2020 - Comments: 5

Leading-edge chipmakers, foundries and EDA companies are pushing into 3nm and beyond, and they are encountering a long list of challenges that raise questions about whether the entire system needs to be shrunk onto a chip or into a package. For 7nm and 5nm, the problems are well understood. In fact, 5nm appears to be more of an evolution from 7nm than a major shift in direction. But at 3nm, ... » read more

Week In Review: Auto, Security, Pervasive Computing

By Susan Rambo - 28 Feb, 2020 - Comments: 0

AI/Edge The United States Department of Defense (DOD) has adopted ethical principles for using artificial intelligence in warfare that chiefly say the U.S. has to follow the laws, treaties, in use of AI in warfare. Any AI used by DOD has to be responsible, equitable, traceable, reliable and governable. “The Department will design and engineer AI capabilities to fulfill their intended functio... » read more

The Challenges Of Building Inferencing Chips

By Ann Mutschler - 27 Feb, 2020 - Comments: 0

Putting a trained algorithm to work in the field is creating a frenzy of activity across the chip world, spurring designs that range from purpose-built specialty processors and accelerators to more generalized extensions of existing and silicon-proven technologies. What's clear so far is that no single chip architecture has been deemed the go-to solution for inferencing. Machine learning is ... » read more

SoC Co-Emulation Using Zynq Boards

By Michelle Mata - 27 Feb, 2020 - Comments: 0

Have you ever worked on a group project where you had to combine your work with that of a colleague of a different engineering discipline but the absence of an efficient means of doing so affected the project’s overall outcome? Well, for software and hardware engineers developing an SoC, the merging of their respective engineering efforts for verification purposes is a big challenge. Early... » read more

The Cost Of Programmability

By Brian Bailey - 27 Feb, 2020 - Comments: 1

Nothing comes for free, and that is certainly true for the programmable elements in an SoC. But without them we are left with very specific devices that can only be used for one fixed application and cannot be updated. Few complex devices are created that do not have many layers of programmability, but the sizing of those capabilities is becoming more important than in the past. There are... » read more

Blog Review: Feb. 26

By Jesse Allen - 26 Feb, 2020 - Comments: 0

Cadence's Paul McLellan listens in as Warren Savage of the University of Maryland explains how security threats are increasing as IoT devices broaden the attack surface and why the semiconductor industry needs to take responsibility. Synopsys' Taylor Armerding argues that a key first step to complying with new and upcoming consumer privacy laws should be ensuring cybersecurity to protect aga... » read more

What’s In Your IP?

By Ed Sperling - 21 Feb, 2020 - Comments: 0

Jeff Markham, software architect at ClioSoft, talks with Semiconductor Engineering about IP traceability in markets such as automotive and aerospace, what’s actually in IP, what should not be in that IP from a security standpoint, and how all of this data can used to avert system reliability issues in the future. » read more

Blog Review: Feb. 19

By Jesse Allen - 19 Feb, 2020 - Comments: 0

Arm's Urmish Thakker takes a look at TinyML, some of the challenges in developing efficient architectures for resource constrained devices, and an explanation of Kronecker product compression. Mentor's Colin Walls considers whether it's better to use single or multiple returns for a function when writing understandable, readable code. Cadence's Paul McLellan shares highlights from a prese... » read more

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Knowledge Centers
Entities, people and technologies explored

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

Legacy Process Nodes Going Strong

The critical, and growing, significance of mature node chips and processes.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

tag: ARM