Blog Review: Sept. 25

By Jesse Allen - 25 Sep, 2019 - Comments: 0

Mentor's Dave Rich points out that unexpected values from a constraint solver can often be explained by how Verilog expression evaluation rules affect the solution space of SystemVerilog constraints. Cadence's Madhavi Rao points to the need for new and updated safety and cybersecurity standards for autonomous vehicles and highlights one of the most challenging parts of AV deployment. A Sy... » read more

Week In Review: Design, Low Power

By Jesse Allen - 20 Sep, 2019 - Comments: 0

Tools & IP Synopsys debuted its new DesignWare ARC EV7x Embedded Vision Processor family for machine learning and AI edge applications. The ARC EV7x Vision Processors integrate up to four enhanced vector processing units (VPUs) and an optional Deep Neural Network (DNN) accelerator with up to 14,080 MACs to deliver up to 35 TOPS performance in 16nm FinFET process technologies under typical ... » read more

Week in Review – IoT, Security, Autos

By Jeff Dorsch - 20 Sep, 2019 - Comments: 0

Products/Services Synopsys had a lot of announcements this week! Summer is definitely over. The company released BSIMM10 study, the latest version of the Building Security in Maturity Model, helping organizations plan, execute, mature, and measure their software security initiatives. It also released LucidShape version 2019.09, the latest version of that tool for the design, simulation, and an... » read more

Blog Review: Sept. 18

By Jesse Allen - 18 Sep, 2019 - Comments: 0

Cadence's Paul McLellan checks out MLPerf and the challenges involved in developing a benchmark to assess machine learning training and inference performance. Synopsys' Om Prakash Thakur and Nusrat Ali take a look at the different types of NVDIMM and how it can bridge the performance gap between memory and storage solutions in servers. Mentor's Matthew Ballance points to why adoption of P... » read more

FPGA Design Tradeoffs Getting Tougher

By Ann Mutschler - 16 Sep, 2019 - Comments: 0

FPGAs are getting larger, more complex, and significantly harder to verify and debug. In the past, FPGAs were considered a relatively quick and simple way to get to market before committing to the cost and time of developing an ASIC. But today, both FPGAs and eFPGAs are being used in the most demanding applications, including cloud computing, AI, machine learning, and deep learning. In some ... » read more

The New CXL Standard

By Ed Sperling - 16 Sep, 2019 - Comments: 0

Gary Ruggles, senior staff product marketing manager at Synopsys, digs into the new Compute Express Link standard, why it’s important for high bandwidth in AI/ML applications, where it came from, and how to apply it in current and future designs. » read more

Week in Review – IoT, Security, Autos

By Jeff Dorsch - 13 Sep, 2019 - Comments: 0

Products/Services Arm and Swift Navigation will collaborate on providing technology to developers of autonomous vehicles and connected cars. San Francisco-based Swift Navigation, which offers Global Navigation Satellite System positioning technology for AVs, is teaming with the chip design company to offer Swift’s solutions as an option on Arm-based platforms, the companies say. Swift’s St... » read more

Week In Review: Design, Low Power

By Jesse Allen - 13 Sep, 2019 - Comments: 0

M&A ANSYS will acquire Livermore Software Technology Corp. (LSTC), a provider of explicit dynamics and other advanced finite element analysis technology. Based in Livermore, CA, LSTC was founded in 1987 to commercialize the DYNA3D technology developed at the Lawrence Livermore National Laboratory. DYNA3D became the company's premier product LS-DYNA, a general purpose nonlinear finite eleme... » read more

3D Power Delivery

By Brian Bailey - 12 Sep, 2019 - Comments: 1

Getting power into and around a chip is becoming a lot more difficult due to increasing power density, but 2.5D and 3D integration are pushing those problems to whole new levels. The problems may even be worse with new packaging approaches, such as chiplets, because they constrain how problems can be analyzed and solved. Add to that list issues around new fabrication technologies and an emph... » read more

Trading Off Power And Performance Earlier In Designs

By Ann Mutschler - 12 Sep, 2019 - Comments: 0

Optimizing performance, power and reliability in consumer electronics is an engineering feat that involves a series of tradeoffs based on gathering as much data about the use cases in which a design will operate. Approaches vary widely by market, by domain expertise, and by the established methodologies and perspective of the design teams. As a result, one team may opt for a leading-edge des... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

Legacy Process Nodes Going Strong

The critical, and growing, significance of mature node chips and processes.

by Bryon Moyer

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

tag: ARM

Blog Review: Sept. 25

Week In Review: Design, Low Power

Week in Review – IoT, Security, Autos

Blog Review: Sept. 18

FPGA Design Tradeoffs Getting Tougher

The New CXL Standard

Week in Review – IoT, Security, Autos

Week In Review: Design, Low Power

3D Power Delivery

Trading Off Power And Performance Earlier In Designs