tag: CD-SEM

Inside Inspection And Metrology
By Mark LaPedus - 18 Dec, 2015 - Comments: 0

Semiconductor Engineering sat down to talk about inspection, metrology and other issues with Mehdi Vaez-Iravani, vice president of advanced imaging technologies at Applied Materials. What follows are excerpts of that conversation. SE: Today, the industry is working on a new range of complex architectures, such as 3D NAND and finFETs. For these technologies, the industry is clearly struggling... » read more

Measuring FinFETs Will Get Harder
By Mark LaPedus - 19 Nov, 2015 - Comments: 2

The industry is gradually migrating toward chips based on finFET transistors at 16nm/14nm and beyond, but manufacturing those finFETs is proving to be a daunting challenge in the fab. Patterning is the most difficult process for finFETs. But another process, metrology, is fast becoming one of the biggest challenges for the next-generation transistor technology. In fact, [getkc id="252" kc_n... » read more

Taming Mask Metrology
By Mark LaPedus - 22 Oct, 2015 - Comments: 0

For years the IC industry has worried about a bevy of issues with the photomask. Mask costs are the top concern, but mask complexity, write times and defect inspection are the other key issues for both optical and EUV photomasks. Now, mask metrology, the science of measuring the key parameters on the mask, is becoming a new challenge. On this front, mask makers are concerned about the critic... » read more

Mask Metrology Challenges Grow
By Mark LaPedus - 29 Sep, 2015 - Comments: 0

Photomasks are becoming more complex at each node. In fact, masks are moving from traditional shapes to non-orthogonal patterns and complex shapes, such as curvilinear mask patterns. To measure patterns and shapes on the mask, photomask makers use traditional critical-dimension scanning electron microscopes (CD-SEMs). In general, the CD-SEM, the workhorse metrology tool in the mask shop, use... » read more

Tech Talk: Wafer Plane Analysis
By Ed Sperling - 23 Jul, 2015 - Comments: 0

Leo Pang, executive vice president at D2S, talks about the problems of patterning at 40nm and below and how to deal with them more effectively using existing equipment. [youtube vid=FbRyhw2q3fE] » read more

Getting Over Overlay
By Mark LaPedus - 18 Jun, 2015 - Comments: 0

Chipmakers continue to migrate to the next node, but there are signs that traditional IC scaling is slowing down. So what’s causing the slowdown? Or for that matter, what could ultimately undo [getkc id="74" comment="Moore's Law"]? It could be a combination of factors. To be sure, IC design costs and complexity are soaring at each node. Scaling challenges are also playing a role. And ov... » read more

10nm Fab Challenges
By Mark LaPedus - 21 May, 2015 - Comments: 1

After a promising start in 2015, the semiconductor equipment industry is currently experiencing a slight lull. The pause is expected to be short-lived, however. Suppliers of [getkc id="208" comment="3D NAND"] devices are expected to add more fab capacity later this year. And about the same time, foundries are expected to order the first wave of high-volume production tools for 10nm. At 10nm... » read more

Waiting For Next-Gen Metrology
By Mark LaPedus - 21 May, 2015 - Comments: 0

Chipmakers continue to march down the various process nodes, but the industry will require new breakthroughs to extend IC scaling at 10nm and beyond. In fact, the industry will require innovations in at least two main areas—patterning and the [getkc id="36" comment="Interconnect"]. There are other areas of concern, but one technology is quickly rising near the top of the list—metrology.... » read more

Flash Dance For Inspection And Metrology
By Mark LaPedus - 16 Apr, 2015 - Comments: 0

Chipmakers are moving from planar technology to an assortment of 3D-like architectures, such as 3D NAND and finFETs For these devices, chipmakers face a multitude of challenges in the fab. But one surprising and oft-forgotten technology is emerging as perhaps the biggest challenge in both logic and memory—process control. Process control includes metrology and wafer inspection. Metrolo... » read more

Searching For 3D Metrology
By Mark LaPedus - 19 Mar, 2015 - Comments: 3

In the previous decade, chipmakers made a bold but necessary decision to select the [getkc id="185" kc_name="finFET"] as the next transistor architecture for the IC industry. Over time, though, chipmakers discovered that the finFET would present some challenges in the fab. Deposition, etch and lithography were the obvious hurdles, but chipmakers also saw a big gap in metrology. In fact,... » read more

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