tag: Cadence

Using Data More Effectively In Chip Manufacturing
By Ed Sperling - 23 Aug, 2023 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss smart manufacturing and how tools and AI can enable it for semiconductors, with Mujtaba Hamid, general manager for product management for secure cloud environments at Microsoft; Vijaykishan Narayanan, vice president and general manager of India engineering and operations at proteanTecs; KT Moore, vice president of corporate ma... » read more

Blog Review: Aug. 23
By Jesse Allen - 23 Aug, 2023 - Comments: 0

Siemens' Stephen Chavez discusses best practices when it comes to thermal analysis for PCB design, including component placement and close collaboration between mechanical and electrical engineering disciplines. Synopsys' Gary Ruggles, Richard Solomon, and Varun Agrawal introduce the Compute Express Link (CXL) specification and how it could help improve latency through computational offloadi... » read more

Week In Review: Design, Low Power
By Susan Rambo - 18 Aug, 2023 - Comments: 0

Synopsys’ board of directors appointed Sassine Ghazi as president and chief executive officer effective on Jan. 1, 2024. Ghazi, who is currently the COO, will succeed Aart de Geus, co-founder, chair, and CEO of Synopsys, who will then become the executive chair of board of directors. IBM Research introduced  an energy-efficient mixed-signal analog AI chip for DNN inferencing and demonstra... » read more

Tradeoffs Between On-Premise And On-Cloud Design
By Ann Mutschler - 16 Aug, 2023 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down discuss how and why companies are dividing up work on-premise and in the cloud, and what to watch out for, with Philip Steinke, fellow, CAD infrastructure and physical design at AMD; Mahesh Turaga, vice president of business development for cloud at Cadence Design Systems; Richard Ho, vice president hardware engineering at Lightmatter; Cr... » read more

Blog Review: Aug. 16
By Jesse Allen - 16 Aug, 2023 - Comments: 0

Synopsys' Johannes Stahl and Tim Kogel suggest that multi-die systems require a new approach at the architecture planning phase and why chip designers can’t ignore physical effects such as layout, power, temperature, or IR-drop. Siemens' Rich Edelman argues for using the waveform window in a GUI rather than $display when debugging UVM. Cadence's Paul Scannell stresses the need for diver... » read more

Why It’s So Difficult To Ensure System Safety Over Time
By Brian Bailey - 14 Aug, 2023 - Comments: 0

Safety is emerging as a concern across an increasing number of industries, but standards and methodologies are not in place to ensure electronic systems attain a defined level of safety over time. Much of this falls on the shoulders of the chip industry, which provides the underlying technology, and it raises questions about what more can be done to improve safety. A crude taxonomy recently ... » read more

Processor Tradeoffs For AI Workloads
By Ann Mutschler - 10 Aug, 2023 - Comments: 0

AI is forcing fundamental shifts in chips used in data centers and in the tools used to design them, but it also is creating gaps between the speed at which that technology advances and the demands from customers. These shifts started gradually, but they have accelerated and multiplied over the past year with the rollout of ChatGPT and other large language models. There is suddenly much more... » read more

MRAM Getting More Attention At Smallest Nodes
By Karen Heyman - 10 Aug, 2023 - Comments: 2

Magneto-resistive RAM (MRAM) appears to be gaining traction at the most advanced nodes, in part because of recent improvements in the memory itself and in part because new markets require solutions for which MRAM may be uniquely qualified. There are still plenty of skeptics when it comes to MRAM, and lots of potential competitors. That has limited MRAM to a niche role over the past couple de... » read more

Cleaning Marine Geometries Has Never Been Easier
By Veena Parthan - 10 Aug, 2023 - Comments: 0

Ship designers and naval architects increasingly use computational fluid dynamics (CFD) tools for more accurate solutions, detailed physics, and quicker results. Marine ship design studies in the past relied mainly on scaled-down models in towing tanks for insights into ship resistance, seakeeping, propulsion, and maneuvering. However, these models had discrepancies in their Reynolds and Fro... » read more

Blog Review: Aug. 9
By Jesse Allen - 09 Aug, 2023 - Comments: 0

Synopsys' John Swanson and Manmeet Walia note that designing for 224G Ethernet will entail some unique considerations, as design margins will be extremely tight, making it mission-critical to optimize individual analog blocks to reduce impairments. Cadence's Rick Sanborn finds that knowing how best to debug common partitioning-related issues and implicitly control them using common features ... » read more

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