Radar-Based Vital Signs Detection For In-Cabin Applications

By Cadence - 10 Oct, 2024 - Comments: 0

Radars have been at the forefront of the automotive industry for some time now. They play an integral part in advanced driver assistance systems (ADAS) and aid in applications such as adaptive cruise control, collision mitigation, blind spot detection, lane change assist, and many other applications. In-cabin sensing is an emerging area in the automotive industry, and radars play an integral... » read more

The Cost Of EDA Data Storage And Processing Efficiency

By Adam Kovac - 09 Oct, 2024 - Comments: 0

Engineering teams are turning to the cloud to process and store increasing amounts of EDA data, but while the compute resources in hyperscale data centers are virtually unlimited, the move can add costs, slow access to data, and raise new concerns about sustainability. For complex chip designs, the elasticity of the cloud is a huge bonus. With advanced-node chips and packaging, the amount of... » read more

Blog Review: Oct. 9

By Liz Allan - 09 Oct, 2024 - Comments: 0

Siemens’ Stephen Chavez looks at the key benefits and challenges to achieving a successful ECAD-MCAD collaboration. Cadence’s Nayan Gaywala shares the AXI4 locking mechanism when implementing an Xtensa LX-based multi-core system on a Xilinx FPGA platform, using a dual-core design mapped to a KC705 platform as an example. Synopsys’ Vincent van der Leest digs into SRAM PUFs and their ... » read more

Government Chip Funding Spreads Globally

By Liz Allan - 07 Oct, 2024 - Comments: 0

This is the first in a series of articles tracking government chip investments. See part two for Americas-focused funding and part three for the UK and EMEA, and part four for Asia. Countries around the world are ramping up investments into their semiconductor industries as part of new or existing approaches. The increased government activity stems from growing awareness of the strategic imp... » read more

Partitioning In The Chiplet Era

By Ann Mutschler - 03 Oct, 2024 - Comments: 0

The widespread adoption of chiplets in domain-specific applications is creating a partitioning challenge that is much more complex than anything chip design teams have dealt with in previous designs. Nearly all the major systems companies, packaging houses, IDMs, and foundries have focused on chiplets as the best path forward to improve performance and reduce power. Signal paths can be short... » read more

Chip Industry Week In Review

By The SE Staff - 27 Sep, 2024 - Comments: 0

Global spending on 300mm fab equipment is expected to reach a record US$400 billion from 2025 to 2027, according to SEMI. Key drivers are the regionalization of semiconductor fabs and the increasing demand for AI chips in data centers and edge devices, with China, South Korea, and Taiwan leading the way. The Biden-Harris Administration launched the National Semiconductor Technology Center’... » read more

Using AI To Glue Disparate IC Ecosystem Data

By Ed Sperling and Ann Mutschler - 26 Sep, 2024 - Comments: 0

AI holds the potential to change how companies interact throughout the global semiconductor ecosystem, gluing together different data types and processes that can be shared between companies that in the past had little or no direct connections. Chipmakers always have used abstraction layers to see the bigger picture of how the various components of a chip go together, allowing them to pinpoi... » read more

DDR5 UDIMM Evolution To Clock Buffered DIMMs (CUDIMM)

By Shyam Sharma - 26 Sep, 2024 - Comments: 0

DDR5 is the latest generation of PCDDR memory that is used in a wide range of application like data centers, Laptops and personal computers, autonomous driving systems, servers, cloud computing, and gaming are now increasingly being used for AI applications with advances in memory bandwidth and density to allow DDR5 DIMMs (Dual Inline Memory Modules) to support densities higher then 256 GB per ... » read more

RAG-Enabled AI Stops Hallucinations, Adds Sources

By Karen Heyman - 26 Sep, 2024 - Comments: 0

Many EDA companies have taken the first steps to incorporate generative AI into their tools, and in such tightly controlled environments GenAI appears to have great benefits. But its broader adoption has been delayed by its notorious inaccuracy, giving results that are often out of date, untrue, and unsourced. That's starting to change. GenAI is evolving so rapidly that these kinds of proble... » read more

Impact of Finite Interconnect Impedance Including Spatial and Domain Comparison of PDN Characterization

By Cadence - 25 Sep, 2024 - Comments: 0

Abstract Over the past few decades, a lot of details have been worked out in power distribution network design, simulation and measurement. We have well-established PDN design procedures both in the frequency and time domains, we have simulation tools that can analyze the physical structure from DC to very high frequencies, including spatial variations of the behavior, and we also have fre... » read more

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Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

New AI Processors Architectures Balance Speed With Efficiency

Hot Chips 24: Large language models ratchet up pressure for sustainable computing and heterogeneous integration; data management becomes key differentiator.

by Ed Sperling

tag: Cadence

Radar-Based Vital Signs Detection For In-Cabin Applications

The Cost Of EDA Data Storage And Processing Efficiency

Blog Review: Oct. 9

Government Chip Funding Spreads Globally

Partitioning In The Chiplet Era

Chip Industry Week In Review

Using AI To Glue Disparate IC Ecosystem Data

DDR5 UDIMM Evolution To Clock Buffered DIMMs (CUDIMM)

RAG-Enabled AI Stops Hallucinations, Adds Sources

Impact of Finite Interconnect Impedance Including Spatial and Domain Comparison of PDN Characterization