tag: chip design

Week In Review: Design, Low Power
By Jesse Allen - 07 Feb, 2020 - Comments: 0

Presto Engineering, an outsourced operations provider to semiconductor and IoT device manufacturers, acquired the DELTA Microelectronics business unit of FORCE Technology. The acquisition adds DELTA's ASIC design and manufacturing to its portfolio. The two companies will retain a strong relationship: FORCE Technology has become a shareholder of Presto Engineering and Juan Farré, FORCE’s CTO,... » read more

Week In Review: Design, Low Power
By Jesse Allen - 24 Jan, 2020 - Comments: 0

Xilinx filed a patent infringement countersuit against Analog Devices, alleging infringement of eight U.S. patents including technologies involving serializers/deserializers (SerDes), high-speed ADCs and DACs, as well as mixed-signal devices targeting 5G and other markets. The counterclaims are in response to Analog Devices' December lawsuit alleging unauthorized use by Xilinx of eight ADI pate... » read more

Dealing With ECOs In Complex Designs
By Ed Sperling - 22 Jan, 2020 - Comments: 0

Namsuk Oh, R&D principal engineer at Synopsys, talks about the impact of more corners and engineering change orders, how that needs to be addressed in the flow to close timing, and how dependencies can complicate any changes that are required. » read more

Priorities Shift In IC Design
By Ann Mutschler - 16 Jan, 2020 - Comments: 0

The rush to the edge and new applications around AI are causing a shift in design strategies toward the highest performance per watt, rather than the highest performance or lowest power. This may sound like hair-splitting, but it has set a scramble in motion around how to process more data more quickly without just relying on faster processors and accelerators. Several factors are driving th... » read more

CEO Outlook: 2020 Vision
By Ed Sperling - 06 Jan, 2020 - Comments: 0

The start of 2020 is looking very different than the start of 2019. Markets that looked hazy at the start of 2019, such as 5G, are suddenly very much in focus. The glut of memory chips that dragged down the overall chip industry in 2019 has subsided. And a finely tuned supply chain that took decades to develop is splintering. A survey of CEOs from across the industry points to several common... » read more

Week In Review: Design, Low Power
By Jesse Allen - 08 Nov, 2019 - Comments: 0

Cadence unveiled a static timing/signal integrity analysis and power integrity analysis tool, Tempus Power Integrity Solution, that integrates the Tempus Timing Signoff and Voltus IC Power Integrity signoff engines. Early use cases demonstrated it correctly identified IR drop errors, avoiding silicon failure prior to tapeout and improving the maximum frequency in silicon by up to 10%. Arasan... » read more

Week In Review: Design, Low Power
By Jesse Allen - 18 Oct, 2019 - Comments: 0

Allegro DVT acquired Amphion Semiconductor, bringing together two developers of video codec IP. Allegro DVT said the merger will make it the first semiconductor IP company to offer commercially available hardware-based, real-time encoder and decoder solutions for the new AV1 video encoding format for SoC implementations, supporting 4K/UHD up to 8K. Based in Belfast, Northern Ireland, Amphion wa... » read more

Week In Review: Design, Low Power
By Jesse Allen - 20 Sep, 2019 - Comments: 0

Tools & IP Synopsys debuted its new DesignWare ARC EV7x Embedded Vision Processor family for machine learning and AI edge applications. The ARC EV7x Vision Processors integrate up to four enhanced vector processing units (VPUs) and an optional Deep Neural Network (DNN) accelerator with up to 14,080 MACs to deliver up to 35 TOPS performance in 16nm FinFET process technologies under typical ... » read more

Week In Review: Design, Low Power
By Jesse Allen - 09 Aug, 2019 - Comments: 0

Synopsys will acquire QTronic GmbH, a provider of simulation, test tools, and services for automotive software and systems development. Based in Germany, QTronic was founded in 2006 and makes a virtual ECU platform as well as a test automation solution with test case generator. Terms of the deal were not disclosed. VeriSilicon uncorked VIP9000, a highly scalable and programmable processor fo... » read more

Are Digital Twins Something For EDA To Pursue?
By Ann Mutschler - 07 Aug, 2019 - Comments: 0

‘Digital Twins’ are one of the new, fashionable key concepts for system developers, but do they fit with EDA? How many different types of engines do these twins run on – abstract simulation, signal-based RTL simulation, emulation, prototyping, actual silicon? What should the use models be called for digital twinning – like reproduction of bugs from silicon in emulation? Or optimizing th... » read more

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