Week In Review: Design, Low Power

Xilinx, Analog Devices patent suits; ARC HS4x/4xD development kit; Intel contributes AIB to CHIPS Alliance.


Xilinx filed a patent infringement countersuit against Analog Devices, alleging infringement of eight U.S. patents including technologies involving serializers/deserializers (SerDes), high-speed ADCs and DACs, as well as mixed-signal devices targeting 5G and other markets. The counterclaims are in response to Analog Devices’ December lawsuit alleging unauthorized use by Xilinx of eight ADI patents relating to converter technology in at least two of Xilinx’s High End Zynq UltraScale+ RFSoC products. In both lawsuits, the companies are asking for damages and injunctions against selling infringing products.

Tools & IP
Synopsys launched the DesignWare ARC HS4x/4xD Development Kit to accelerate software development for the ARC HS4x/4xD family of high-performance processor IP. The platform supports the Linux kernel and access to embARC open-source software packages. The Development Kit includes a multicore ARC HS4x/HS4xD-based chip implemented in a 28nm process, and integrates a range of interfaces including Ethernet, HDMI, USB, SDIO, I2C, SPI, UART, and GPIO, as well as a low-power GPU. The kit also features an on-board WiFi (802.11abgn) and Bluetooth (BT4.0) module. It is configurable to support single and dual-core HS45D and HS47D processors and up to quad-core ARC HS48 processors.

CAST debuted a new IP core implementing a switched endpoint controller supporting the Time-Sensitive Networking (TSN) Ethernet standards. The TSN-SE TSN Ethernet Switched Endpoint Controller IP core integrates hardware stacks for timing synchronization (IEEE 802.1AS), traffic shaping (IEEE 802.1Qav and IEEE 802.1Qbv), frame-preemption (IEEE 802.1Qbu and IEEE 802.1Qbr), and a low-latency Ethernet MAC.

Allegro DVT uncorked compliance test bitstreams for the new Versatile Video Coding (VVC) video standard, the next video compression technology beyond H.265/HEVC.

sureCore is offering its low power memory compiler for 30 days to qualifying companies to evaluate the capabilities of their PowerMiser and EverOn standard SRAM IP products on low power metrics, using 22nm, 28nm or 40nm process technology.

Intel joined the CHIPS Alliance, a consortium advancing common and open hardware for interfaces, processors and systems. Intel is contributing the Advanced Interface Bus (AIB) as an open-source, royalty-free PHY-level standard for connecting multiple semiconductor die within the same package. The company and consortium hope to encourage development and use of chiplets. Intel will have a seat on the governing board of CHIPS Alliance.

Vastai Technologies licensed Arteris IP’s FlexNoC Interconnect IP and the accompanying AI Package for use in its next-generation AI and computer vision SoC. Vastai cited reduced product costs and a shortened development schedule while achieving better performance than expected, as well as support.

Synopsys will establish an application security validation program for Finastra’s FusionFabric.cloud, an open platform for developing, deploying and consuming financial/Fintech applications. The program will ensure that all applications offered via the FusionFabric.cloud FusionStore have passed thorough vigorous security testing assessments including static application security testing, software composition analysis, penetration testing, and code reviews.

Market research firm IC Insights predicts that 26 of 33 IC product categories will see positive growth in 2020, with a forecast growth of 8% for the entire IC market. DRAM and NAND are both expected to see strong rebounds in the coming year. Automotive special purpose logic and embedded MCUs are also expected to continue strong growth.

Check out upcoming industry events and conferences: DesignCon will take place Jan. 28-30 in Santa Clara, CA, with a focus on board and high-speed communications design. FPGA 2020 will be held Feb. 23-25 in Seaside, CA, and includes sessions on deep learning, architectures, tools, and security. DVCon is Mar. 2-5 in San Jose, CA; key topics include formal verification, Portable Stimulus, IP security, intelligent system design, AI and ML-focused verification, 5G verification, UVM strategies, power-aware design and hybrid verification. Plus, nominations for the Marie R. Pistilli Women in EDA award are open; DAC will be co-located with SEMICon West July 19-23, 2020 in San Francisco, CA.

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