Week In Review: Design, Low Power

AI for chip optimization; TensorFlow Lite on DSPs; RISC-V trace spec; CMC supports L-UTSOI model.


Tools & IP
Synopsys revealed DSO.ai (Design Space Optimization AI), an autonomous AI application that searches for optimization targets in very large solution spaces of chip design, inspired by the process of DeepMind’s game-playing AlphaZero. DSO.ai engines ingest large data streams generated by chip design tools and use them to explore search spaces, observing how a design evolves over time and adjusting design choices, technology parameters, and workflows to guide the exploration process towards multi-dimensional optimization objectives. It also automates less consequential decisions, like tuning tool settings. Samsung cited improved PPA results in a shorter time. Broader availability is expected in the second half of the year.

Software for Cadence’s Tensilica HiFi DSPs has been optimized to efficiently execute TensorFlow Lite for Microcontrollers, aiming to promote rapid development of edge applications that use AI and ML and remove the need to hand-code the neural networks.

Synopsys also updated its Simpleware ScanIP software, a solution for 3D image processing and segmenting images generated by computed tomography (CT) or MRI scanners. The new module adds ML-based auto segmentation for knees and hips, speeding segmentation time.

The RISC-V Foundation ratified the RISC-V ISA processor trace specification, which enables viewing of exactly what instructions a core is executing, step by step. It includes filtering capabilities to isolate the trace portions that matter.

The Si2 Compact Model Coalition will provide financial support for L-UTSOI, a new ultra-thin, silicon-on-insulator transistor simulation model developed by CEA-Leti. Members of CMC noted the model’s physically based model parameters, ability to simulate a wide range of voltages and body biases, and accurate modeling of ultra-thin body and box fully-depleted SOI devices.

STMicroelectronics teamed up with Cadence to tape out a 56G very short-reach (VSR) SerDes in 7nm for a SoC targeted at the networking, cloud and data center markets. Cadence provided critical IP architecture and certain IP sub-blocks while ST developed the complete SerDes core.

Alphawave adopted the Synopsys Custom Design Platform to accelerate the design of multi-standard connectivity IP. The companies built a customized regression system that automatically generates simulation jobs, compares results with previous runs, and reports failures. Alphawave also deployed Synopsys’ Custom Compiler Quick Start Kits.

The EDF Group will use Ansys’ multiphysics solutions in the design of state-of-the-art nuclear power plants, in particular advanced plant instrumentation and controls. The two companies previously worked together in the ConnexITy R&D program for nuclear plants.

Cadence and Dover Microsystems are working together on secure embedded processors by integrating Dover’s CoreGuard technology and the Cadence Tensilica Xtensa LX7 processor. CoreGuard monitors each executed instruction to ensure it complies with a set of security, safety and privacy rules and stops violating instructions.

L3Harris Technologies and Ansys are working with the U.S. Army through a Cooperative Research and Development Agreement (CRADA) to develop software aligned with the FACE Technical Standard, which aims to make software on embedded military computing systems to be more interoperable, portable and secure. The CRADA has utilized software from the two companies on the Crew Mission System platform for the Cockpit Display Station.

Events and Videos
Many conferences have now been cancelled, postposed, or moved online. Find out what’s happening with each at our events page. How about checking out a webinar instead?  Also, videos of the week include Visualizing Differences In Analog Design and High-Performance Memory For AI & HPC.

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